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| www.motorola.com/semiconductors m68hc08 microcontrollers mc68HC908LJ12/d rev. 2, 2/2002 mc68HC908LJ12 technical data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola technical data 3 mc68HC908LJ12 technical data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola, inc. is an equal opportunity/affirmative action employer. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. ? motorola, inc., 2002 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data technical data mc68HC908LJ12 ? rev. 2.0 4 technical data motorola to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) february 2002 2 first general release. ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola list of sections 5 technical data ? mc68HC908LJ12 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 33 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 43 section 3. random-access memory (ram) . . . . . . . . . . 59 section 4. flash memory (flash) . . . . . . . . . . . . . . . . 61 section 5. configuration registers (config) . . . . . . . . 71 section 6. central processor unit (cpu) . . . . . . . . . . . . 77 section 7. oscillator (osc) . . . . . . . . . . . . . . . . . . . . . . . 95 section 8. clock generator module (cgm) . . . . . . . . . . 101 section 9. system integration module (sim) . . . . . . . . 131 section 10. monitor rom (mon) . . . . . . . . . . . . . . . . . . 155 section 11. timer interface module (tim) . . . . . . . . . . . 185 section 12. real time clock (rtc) . . . . . . . . . . . . . . . . 209 section 13. infrared serial communications interface module (irsci) . . . . . . . . . . . . 227 section 14. serial peripheral interface module (spi) . . 269 section 15. analog-to-digital converter (adc) . . . . . . 301 section 16. liquid crystal display driver (lcd) . . . . . 317 section 17. input/output (i/o) ports . . . . . . . . . . . . . . . 341 section 18. external interrupt (irq) . . . . . . . . . . . . . . . 357 section 19. keyboard interrupt module (kbi). . . . . . . . 363 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections technical data mc68HC908LJ12 ? rev. 2.0 6 list of sections motorola section 20. computer operating properly (cop) . . . . 371 section 21. low-voltage inhibit (lvi) . . . . . . . . . . . . . . 377 section 22. break module (brk) . . . . . . . . . . . . . . . . . . 383 section 23. electrical specifications. . . . . . . . . . . . . . . 391 section 24. mechanical specifications . . . . . . . . . . . . . 407 section 25. ordering information . . . . . . . . . . . . . . . . . 411 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola table of contents 7 technical data ? mc68HC908LJ12 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.6.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . 40 1.6.2 analog power supply pin (v dda ) . . . . . . . . . . . . . . . . . . . . . 40 1.6.3 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 41 1.6.4 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.6.5 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.6.6 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . 41 1.6.7 adc voltage high reference pin (v refh ). . . . . . . . . . . . . . 41 1.6.8 adc voltage low reference pin (v refl ) . . . . . . . . . . . . . . 41 1.6.9 port a input/output (i/o) pins (pta7 ? pta0) . . . . . . . . . . . . 42 1.6.10 port b i/o pins (ptb7 ? ptb0) . . . . . . . . . . . . . . . . . . . . . . .42 1.6.11 port c i/o pins (ptc7 ? ptc0) . . . . . . . . . . . . . . . . . . . . . . . 42 1.6.12 port d i/o pins (ptd7 ? ptd0) . . . . . . . . . . . . . . . . . . . . . . . 42 1.6.13 lcd backplane and frontplane (bp0 ? bp2, fp0/bp3, fp1 ? fp18). . . . . . . . . . . . . . . . . .42 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . .43 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68HC908LJ12 ? rev. 2.0 8 table of contents motorola 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . .44 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 section 4. flash memory (flash) 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 4.5 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.8.1 flash block protect register . . . . . . . . . . . . . . . . . . . . . . .68 section 5. configuration registers (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.4 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . .73 5.5 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . . .75 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC908LJ12 ? rev. 2.0 technical data motorola table of contents 9 section 6. central processor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .82 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . .84 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 6.7 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 section 7. oscillator (osc) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.3 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.4 crystal (x-tal) oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 98 7.5.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . 98 7.5.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 98 7.5.4 internal rc clock (iclk) . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.5.5 cgm oscillator clock (cgmxclk) . . . . . . . . . . . . . . . . . . . 98 7.5.6 cgm reference clock (cgmrclk) . . . . . . . . . . . . . . . . . . 98 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68HC908LJ12 ? rev. 2.0 10 table of contents motorola 7.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.7 oscillator during break mode. . . . . . . . . . . . . . . . . . . . . . . . . . 99 section 8. clock generator module (cgm) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.1 oscillator module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.4.2 phase-locked loop circuit (pll) . . . . . . . . . . . . . . . . . . .106 8.4.3 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.4.4 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . .108 8.4.5 manual and automatic pll bandwidth modes. . . . . . . . . .108 8.4.6 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 8.4.7 special programming exceptions . . . . . . . . . . . . . . . . . . .114 8.4.8 base clock selector circuit . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.9 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . 115 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.5.1 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . 116 8.5.2 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . .116 8.5.3 pll analog ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . 116 8.5.4 oscillator output frequency signal (cgmxclk) . . . . . . . 116 8.5.5 cgm reference clock (cgmrclk) . . . . . . . . . . . . . . . . . 116 8.5.6 cgm vco clock output (cgmvclk) . . . . . . . . . . . . . . . . 117 8.5.7 cgm base clock output (cgmout). . . . . . . . . . . . . . . . . 117 8.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 117 8.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 8.6.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 8.6.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . . 120 8.6.3 pll multiplier select registers . . . . . . . . . . . . . . . . . . . . . 122 8.6.4 pll vco range select register . . . . . . . . . . . . . . . . . . . . 123 8.6.5 pll reference divider select register . . . . . . . . . . . . . . . 124 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC908LJ12 ? rev. 2.0 technical data motorola table of contents 11 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.8 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 8.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 8.8.3 cgm during break interrupts. . . . . . . . . . . . . . . . . . . . . . . 126 8.9 acquisition/lock time specifications . . . . . . . . . . . . . . . . . . .127 8.9.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . . 127 8.9.2 parametric influences on reaction time . . . . . . . . . . . . . . 127 8.9.3 choosing a filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 section 9. system integration module (sim) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 134 9.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.3.2 clock start-up from por or lvi reset. . . . . . . . . . . . . . . . 135 9.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . .136 9.4 reset and system initialization. . . . . . . . . . . . . . . . . . . . . . . . 136 9.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.4.2 active resets from internal sources . . . . . . . . . . . . . . . . . 137 9.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.4.2.2 computer operating properly (cop) reset. . . . . . . . . . 139 9.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 140 9.4.2.6 monitor mode entry module reset (modrst) . . . . . . . 140 9.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.5.1 sim counter during power-on reset . . . . . . . . . . . . . . . . 141 9.5.2 sim counter during stop mode recovery . . . . . . . . . . . . . 141 9.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . .141 9.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68HC908LJ12 ? rev. 2.0 12 table of contents motorola 9.6.1.3 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . 145 9.6.1.4 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . 145 9.6.1.5 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . 147 9.6.1.6 interrupt status register 3 . . . . . . . . . . . . . . . . . . . . . . . 147 9.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.6.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 9.6.4 status flag protection in break mode . . . . . . . . . . . . . . . .148 9.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 9.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 9.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.8.1 sim break status register . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.8.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . 153 9.8.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . 154 section 10. monitor rom (mon) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 10.4.3 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 10.4.4 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10.6 rom-resident routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 10.6.1 prgrnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 10.6.2 erarnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.6.3 ldrnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 10.6.4 mon_prgrnge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 10.6.5 mon_erarnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 10.6.6 mon_ldrnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 10.6.7 ee_write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 10.6.8 ee_read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC908LJ12 ? rev. 2.0 technical data motorola table of contents 13 section 11. timer interface module (tim) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 192 11.5.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . .193 11.5.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . .193 11.5.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . 194 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . .195 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 11.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 198 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.10.1 tim status and control register . . . . . . . . . . . . . . . . . . . .200 11.10.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 11.10.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . 203 11.10.4 tim channel status and control registers . . . . . . . . . . . .204 11.10.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 section 12. real time clock (rtc) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68HC908LJ12 ? rev. 2.0 14 table of contents motorola 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12.4.1 time functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.4.2 calendar functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.4.3 alarm functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.4.4 timebase interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.4.5 chronograph functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 12.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 12.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.6 rtc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.6.1 rtc control register 1 (rtccr1) . . . . . . . . . . . . . . . . . . 216 12.6.2 rtc control register 2 (rtccr2) . . . . . . . . . . . . . . . . . . 218 12.6.3 rtc status register (rtcsr). . . . . . . . . . . . . . . . . . . . . .219 12.6.4 alarm minute and hour registers (almr and alhr) . . . .222 12.6.5 second register (secr) . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12.6.6 minute register (minr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12.6.7 hour register (hrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12.6.8 day register (dayr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 12.6.9 month register (mthr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.6.10 year register (yrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.6.11 day-of-week register (dowr) . . . . . . . . . . . . . . . . . . . . 226 12.6.12 chronograph data register (chrr) . . . . . . . . . . . . . . . . . 226 section 13. infrared serial communications interface module (irsci) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 13.5 irsci module overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 13.6 infrared functional description. . . . . . . . . . . . . . . . . . . . . . . . 232 13.6.1 infrared transmit encoder . . . . . . . . . . . . . . . . . . . . . . . . . 233 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC908LJ12 ? rev. 2.0 technical data motorola table of contents 15 13.6.2 infrared receive decoder . . . . . . . . . . . . . . . . . . . . . . . . . 233 13.7 sci functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 13.7.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 13.7.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 13.7.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 13.7.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 237 13.7.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 13.7.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 13.7.2.5 transmitter interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 239 13.7.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 13.7.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 13.7.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . .241 13.7.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 13.7.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 13.7.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .243 13.7.3.6 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 13.7.3.7 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 13.7.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 13.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 13.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 13.9 sci during break module interrupts. . . . . . . . . . . . . . . . . . . . 249 13.10 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.10.1 ptb0/txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . 249 13.10.2 ptb1/rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.11 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.11.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.11.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13.11.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 13.11.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 13.11.5 sci status register 2 (scs2) . . . . . . . . . . . . . . . . . . . . . . 262 13.11.6 sci data register (scdr). . . . . . . . . . . . . . . . . . . . . . . . . 263 13.11.7 sci baud rate register (scbr) . . . . . . . . . . . . . . . . . . . . 264 13.11.8 sci infrared control register . . . . . . . . . . . . . . . . . . . . . . . 267 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68HC908LJ12 ? rev. 2.0 16 table of contents motorola section 14. serial peripheral interface module (spi) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 14.4 pin name conventions and i/o register addresses . . . . . . . 271 14.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 14.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 14.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 14.6 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 14.6.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . 275 14.6.2 transmission format when cpha = 0 . . . . . . . . . . . . . . . 276 14.6.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . 278 14.6.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . 279 14.7 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . 281 14.8 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 14.8.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 14.8.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 14.9 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 14.10 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.11 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 14.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 14.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 14.12 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .290 14.13 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 14.13.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . . . 291 14.13.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . . . 291 14.13.3 spsck (serial clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 14.13.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14.13.5 cgnd (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 14.14 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14.14.1 spi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC908LJ12 ? rev. 2.0 technical data motorola table of contents 17 14.14.2 spi status and control register . . . . . . . . . . . . . . . . . . . .296 14.14.3 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 section 15. analog-to-digital converter (adc) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 15.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 15.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 15.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 15.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 15.4.5 result justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 15.4.6 monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 15.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 15.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 15.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 15.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 15.7.1 adc voltage in (v adin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 15.7.2 adc analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . 309 15.7.3 adc voltage reference high pin (v refh ). . . . . . . . . . . . . 309 15.7.4 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . 309 15.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 15.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . . 310 15.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 15.8.3 adc clock control register. . . . . . . . . . . . . . . . . . . . . . . . 314 section 16. liquid crystal display driver (lcd) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68HC908LJ12 ? rev. 2.0 18 table of contents motorola 16.4 pin name conventions and i/o register addresses . . . . . . . 318 16.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 16.5.1 lcd duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 16.5.2 lcd voltages (v lcd , v lcd1 , v lcd2 , v lcd3 ) . . . . . . . . . . . 323 16.5.3 lcd cycle frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 16.5.4 fast charge and low current . . . . . . . . . . . . . . . . . . . . . . 324 16.5.5 contrast control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 16.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 16.7.1 bp0 ? bp3 (backplane drivers) . . . . . . . . . . . . . . . . . . . . . .326 16.7.2 fp0 ? fp26 (frontplane drivers) . . . . . . . . . . . . . . . . . . . . . 328 16.8 seven segment display connection . . . . . . . . . . . . . . . . . . .332 16.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.9.1 lcd control register (lcdcr) . . . . . . . . . . . . . . . . . . . . . 335 16.9.2 lcd clock register (lcdclk) . . . . . . . . . . . . . . . . . . . . . 337 16.9.3 lcd data registers (ldat1 ? ldat14) . . . . . . . . . . . . . . . 339 section 17. input/output (i/o) ports 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 17.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 17.3.1 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . 344 17.3.2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 345 17.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 17.4.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 347 17.4.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 348 17.4.3 port b led control register (ledb) . . . . . . . . . . . . . . . . . 350 17.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 17.5.1 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . 351 17.5.2 data direction register c (ddrc). . . . . . . . . . . . . . . . . . . 352 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC908LJ12 ? rev. 2.0 technical data motorola table of contents 19 17.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 17.6.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 354 17.6.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 355 section 18. external interrupt (irq) 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 18.4.1 irq pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 18.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . .361 18.6 irq status and control register (intscr) . . . . . . . . . . . . . . 361 section 19. keyboard interrupt module (kbi) 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 19.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 19.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 19.5.1 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 19.6 keyboard interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . 367 19.6.1 keyboard status and control register. . . . . . . . . . . . . . . . 368 19.6.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 369 19.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 19.8 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 19.9 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370 19.10 keyboard module during break interrupts . . . . . . . . . . . . . . .370 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68HC908LJ12 ? rev. 2.0 20 table of contents motorola section 20. computer operating properly (cop) 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 20.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 20.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 20.4.1 iclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 20.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 20.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 20.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 20.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 20.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 20.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 20.4.8 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . 374 20.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 20.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 20.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 20.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375 20.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 20.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376 20.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . .376 section 21. low-voltage inhibit (lvi) 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 21.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 21.4.1 interrupt lvi operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 21.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 21.4.3 voltage hysteresis protection . . . . . . . . . . . . . . . . . . . . . . 380 21.4.4 lvi trip selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 21.5 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC908LJ12 ? rev. 2.0 technical data motorola table of contents 21 21.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 21.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 21.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 section 22. break module (brk) 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 22.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 22.4.1 flag protection during break interrupts . . . . . . . . . . . . . . .386 22.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 386 22.4.3 tim1 and tim2 during break interrupts. . . . . . . . . . . . . . .386 22.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 386 22.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386 22.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 22.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 22.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 22.6.1 break status and control register. . . . . . . . . . . . . . . . . . .387 22.6.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . .388 22.6.3 sim break status register . . . . . . . . . . . . . . . . . . . . . . . . . 388 22.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . .390 section 23. electrical specifications 23.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 23.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .392 23.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 393 23.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 23.6 5.0v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 394 23.7 3.3v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 396 23.8 5.0v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68HC908LJ12 ? rev. 2.0 22 table of contents motorola 23.9 3.3v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 23.10 5.0v oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . 398 23.11 3.3v oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . 398 23.12 5.0v adc electrical characteristics . . . . . . . . . . . . . . . . . . . . 399 23.13 3.3v adc electrical characteristics . . . . . . . . . . . . . . . . . . . . 400 23.14 timer interface module characteristics . . . . . . . . . . . . . . . . . 401 23.15 cgm electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . 401 23.16 5.0v spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 23.17 3.3v spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 23.18 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 406 section 24. mechanical specifications 24.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 24.3 52-pin low-profile quad flat pack (lqfp) . . . . . . . . . . . . . . 408 24.4 64-pin low-profile quad flat pack (lqfp) . . . . . . . . . . . . . . 409 24.5 64-pin quad flat pack (qfp). . . . . . . . . . . . . . . . . . . . . . . . . 410 section 25. ordering information 25.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 25.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola list of figures 23 technical data ? mc68HC908LJ12 list of figures figure title page 1-1 mc68HC908LJ12 block diagram. . . . . . . . . . . . . . . . . . . . . . .37 1-2 64-pin qfp and 64-pin lqfp pin assignment . . . . . . . . . . . . 38 1-3 52-pin lqfp pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . .39 1-4 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2-2 control, status, and data registers . . . . . . . . . . . . . . . . . . . . . 46 4-1 flash i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . 62 4-2 flash control register (flcr) . . . . . . . . . . . . . . . . . . . . . . . 63 4-3 flash programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . 67 4-4 flash block protect register (flbpr). . . . . . . . . . . . . . . . . . 68 4-5 flash block protect start address . . . . . . . . . . . . . . . . . . . . . 68 5-1 config registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5-2 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . .73 5-3 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . . .75 6-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 6-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 82 7-1 oscillator module block diagram . . . . . . . . . . . . . . . . . . . . . . . 96 8-1 cgm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8-2 cgm i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . 105 8-3 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . . .115 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data mc68HC908LJ12 ? rev. 2.0 24 list of figures motorola figure title page 8-4 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . . . 118 8-5 pll bandwidth control register (pbwcr) . . . . . . . . . . . . . . 121 8-6 pll multiplier select register high (pmsh) . . . . . . . . . . . . . 122 8-7 pll multiplier select register low (pmsl) . . . . . . . . . . . . . . 122 8-8 pll vco range select register (pmrs) . . . . . . . . . . . . . . . 123 8-9 pll reference divider select register (pmds) . . . . . . . . . . 124 8-10 pll filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 9-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9-2 sim i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9-3 cgm clock signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9-6 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9-8 interrupt entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9-9 interrupt recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9-10 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . 144 9-12 interrupt status register 1 (int1). . . . . . . . . . . . . . . . . . . . . .145 9-13 interrupt status register 2 (int2). . . . . . . . . . . . . . . . . . . . . .147 9-14 interrupt status register 3 (int3). . . . . . . . . . . . . . . . . . . . . .147 9-15 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 9-16 wait recovery from interrupt or break . . . . . . . . . . . . . . . . . . 150 9-17 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . 150 9-18 stop mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 9-19 stop mode recovery from interrupt or break . . . . . . . . . . . . . 151 9-20 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . . .152 9-21 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . . . 153 9-22 sim break flag control register (sbfcr) . . . . . . . . . . . . . . 154 10-1 monitor mode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10-2 low-voltage monitor mode entry flowchart. . . . . . . . . . . . . . 162 10-3 monitor data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10-4 break transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10-5 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures mc68HC908LJ12 ? rev. 2.0 technical data motorola list of figures 25 figure title page 10-6 write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 10-7 stack pointer at monitor mode entry . . . . . . . . . . . . . . . . . . .168 10-8 monitor mode entry timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10-9 data block format for rom-resident routines. . . . . . . . . . . 172 10-10 ee_write flash memory usage . . . . . . . . . . . . . . . . . . . . 181 11-1 tim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11-2 tim i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11-3 pwm period and pulse width . . . . . . . . . . . . . . . . . . . . . . . . 194 11-4 tim status and control register (tsc) . . . . . . . . . . . . . . . . . 200 11-5 tim counter registers high (tcnth) . . . . . . . . . . . . . . . . . . 202 11-6 tim counter registers low (tcntl) . . . . . . . . . . . . . . . . . . . 202 11-7 tim counter modulo register high (tmodh) . . . . . . . . . . . .203 11-8 tim counter modulo register low (tmodl) . . . . . . . . . . . . . 203 11-9 tim channel 0 status and control register (tsc0) . . . . . . . 204 11-10 tim channel 1 status and control register (tsc1) . . . . . . . 204 11-11 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 11-12 tim channel 0 register high (tch0h) . . . . . . . . . . . . . . . . . 208 11-13 tim channel 0 register low (tch0l) . . . . . . . . . . . . . . . . . . 208 11-14 tim channel 1 register high (tch1h) . . . . . . . . . . . . . . . . . 208 11-15 tim channel 1 register low (tch1l) . . . . . . . . . . . . . . . . . . 208 12-1 rtc i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . .210 12-2 rtc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 12-3 rtc control register 1 (rtccr1) . . . . . . . . . . . . . . . . . . . . 216 12-4 rtc control register 2 (rtccr2) . . . . . . . . . . . . . . . . . . . . 218 12-5 rtc status register (rtcsr) . . . . . . . . . . . . . . . . . . . . . . . . 219 12-6 alarm minute register (almr). . . . . . . . . . . . . . . . . . . . . . . . 222 12-7 alarm hour register (alhr) . . . . . . . . . . . . . . . . . . . . . . . . . 222 12-8 second register (secr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12-9 minute register (minr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12-10 hour register (hrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12-11 day register (dayr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12-12 month register (mthr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12-13 year register (yrr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12-14 day-of-week register (dowr). . . . . . . . . . . . . . . . . . . . . . . 226 12-15 chronograph data register (chrr) . . . . . . . . . . . . . . . . . . .226 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data mc68HC908LJ12 ? rev. 2.0 26 list of figures motorola figure title page 13-1 irsci i/o registers summary . . . . . . . . . . . . . . . . . . . . . . . . 230 13-2 irsci block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 13-3 infrared sub-module diagram . . . . . . . . . . . . . . . . . . . . . . . . 232 13-4 infrared sci data example. . . . . . . . . . . . . . . . . . . . . . . . . . . 233 13-5 sci module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 234 13-6 sci data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 13-7 sci transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 13-8 sci receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 240 13-9 receiver data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 13-10 slow data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 13-11 fast data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 13-12 sci control register 1 (scc1). . . . . . . . . . . . . . . . . . . . . . . .251 13-13 sci control register 2 (scc2). . . . . . . . . . . . . . . . . . . . . . . .254 13-14 sci control register 3 (scc3). . . . . . . . . . . . . . . . . . . . . . . .256 13-15 sci status register 1 (scs1) . . . . . . . . . . . . . . . . . . . . . . . . 258 13-16 flag clearing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 13-17 sci status register 2 (scs2) . . . . . . . . . . . . . . . . . . . . . . . . 262 13-18 sci data register (scdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 13-19 sci baud rate register (scbr) . . . . . . . . . . . . . . . . . . . . . . 264 13-20 sci infrared control register (scircr) . . . . . . . . . . . . . . . . 267 14-1 spi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 14-2 spi module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 272 14-3 full-duplex master-slave connections . . . . . . . . . . . . . . . . . 273 14-4 transmission format (cpha = 0) . . . . . . . . . . . . . . . . . . . . . 277 14-5 cpha/ss timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 14-6 transmission format (cpha = 1) . . . . . . . . . . . . . . . . . . . . . 278 14-7 transmission start delay (master) . . . . . . . . . . . . . . . . . . . . . 280 14-8 sprf/spte cpu interrupt timing . . . . . . . . . . . . . . . . . . . . . 281 14-9 missed read of overflow condition . . . . . . . . . . . . . . . . . . . . 283 14-10 clearing sprf when ovrf interrupt is not enabled . . . . . . 284 14-11 spi interrupt request generation . . . . . . . . . . . . . . . . . . . . . 287 14-12 cpha/ss timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14-13 spi control register (spcr) . . . . . . . . . . . . . . . . . . . . . . . . . 294 14-14 spi status and control register (spscr) . . . . . . . . . . . . . . .296 14-15 spi data register (spdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures mc68HC908LJ12 ? rev. 2.0 technical data motorola list of figures 27 figure title page 15-1 adc i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . .303 15-2 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 15-3 8-bit truncation mode error . . . . . . . . . . . . . . . . . . . . . . . . . . 307 15-4 adc status and control register (adscr) . . . . . . . . . . . . . . 310 15-5 adrh and adrl in 8-bit truncated mode. . . . . . . . . . . . . . .312 15-6 adrh and adrl in right justified mode. . . . . . . . . . . . . . . . 312 15-7 adrh and adrl in left justified mode . . . . . . . . . . . . . . . . . 313 15-8 adrh and adrl in left justified sign data mode . . . . . . . . 313 15-9 adc clock control register (adiclk). . . . . . . . . . . . . . . . . . 314 16-1 lcd i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . .319 16-2 lcd block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 16-3 simplified lcd schematic (1/3 duty, 1/3 bias) . . . . . . . . . . . 322 16-4 fast charge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 16-5 1/3 duty lcd backplane driver waveforms. . . . . . . . . . . . . . 326 16-6 static lcd backplane driver waveform. . . . . . . . . . . . . . . . . 327 16-7 1/4 duty lcd backplane driver waveforms. . . . . . . . . . . . . . 327 16-8 static lcd frontplane driver waveforms. . . . . . . . . . . . . . . . 328 16-9 1/3 duty lcd frontplane driver waveforms . . . . . . . . . . . . . 329 16-10 1/4 duty lcd frontplane driver waveforms . . . . . . . . . . . . . 330 16-11 1/4 duty lcd frontplane driver waveforms (continued) . . . . 331 16-12 7-segment display example . . . . . . . . . . . . . . . . . . . . . . . . .332 16-13 bp0 ? bp2 and fp0 ? fp2 output waveforms for 7-segment display example . . . . . . . . . . . . . . . . . . . . . . . 333 16-14 "f" segment voltage waveform . . . . . . . . . . . . . . . . . . . . . . .334 16-15 "e" segment voltage waveform . . . . . . . . . . . . . . . . . . . . . . .334 16-16 lcd control register (lcdcr) . . . . . . . . . . . . . . . . . . . . . . . 335 16-17 lcd clock register (lcdclk). . . . . . . . . . . . . . . . . . . . . . . . 337 16-18 lcd data registers 1 ? 14 (ldat1 ? ldat14) . . . . . . . . . . . . . 339 17-1 i/o port register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 342 17-2 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . . .344 17-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 345 17-4 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 17-5 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . . .347 17-6 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 349 17-7 port b i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data mc68HC908LJ12 ? rev. 2.0 28 list of figures motorola figure title page 17-8 port b led control register (ledb) . . . . . . . . . . . . . . . . . . .350 17-9 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . . .351 17-10 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 352 17-11 port c i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 17-12 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . . .354 17-13 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . 355 17-14 port d i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 18-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .359 18-2 irq status and control register (intscr) . . . . . . . . . . . . . . 362 19-1 kbi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 19-2 keyboard interrupt block diagram . . . . . . . . . . . . . . . . . . . . . 365 19-3 keyboard status and control register (kbscr) . . . . . . . . . . 368 19-4 keyboard interrupt enable register (kbier) . . . . . . . . . . . . . 369 20-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 20-2 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . .374 20-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . .375 21-1 lvi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 21-2 lvi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 22-1 break module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 385 22-2 break module i/o register summary . . . . . . . . . . . . . . . . . . . 385 22-3 break status and control register (brkscr). . . . . . . . . . . . 387 22-4 break address register high (brkh) . . . . . . . . . . . . . . . . . . 388 22-5 break address register low (brkl) . . . . . . . . . . . . . . . . . . . 388 22-6 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . . . 389 22-7 sim break flag control register (sbfcr) . . . . . . . . . . . . . . 390 23-1 spi master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404 23-2 spi slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 24-1 52-pin low-profile quad flat pack (case no. 848d). . . . . . . 408 24-2 64-pin low-profile quad flat pack (case no. 840f) . . . . . . . 409 24-3 64-pin quad flat pack (case no. 840b) . . . . . . . . . . . . . . . . 410 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola list of tables 29 technical data ? mc68HC908LJ12 list of tables table title page 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 5-1 lvi trip point selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8-1 numeric examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 8-3 vpr1 and vpr0 programming . . . . . . . . . . . . . . . . . . . . . . . 120 8-2 pre 1 and pre0 programming . . . . . . . . . . . . . . . . . . . . . . . 120 9-1 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 9-3 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 10-1 monitor mode signal requirements and options . . . . . . . . . . 160 10-2 mode differences (vectors) . . . . . . . . . . . . . . . . . . . . . . . . . .162 10-3 monitor baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . 164 10-4 read (read memory) command . . . . . . . . . . . . . . . . . . . . . 165 10-5 write (write memory) command. . . . . . . . . . . . . . . . . . . . . 166 10-6 iread (indexed read) command . . . . . . . . . . . . . . . . . . . . . 166 10-7 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . . . 167 10-8 readsp (read stack pointer) command . . . . . . . . . . . . . . .167 10-9 run (run user program) command . . . . . . . . . . . . . . . . . . . 168 10-10 summary of rom-resident routines . . . . . . . . . . . . . . . . . . 171 10-11 prgrnge routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 10-12 erarnge routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10-13 ldrnge routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 10-14 mon_prgrnge routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 10-15 mon_erarnge routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables technical data mc68HC908LJ12 ? rev. 2.0 30 list of tables motorola table title page 10-16 icp_ldrnge routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 10-17 ee_write routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 10-18 ee_read routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 11-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 11-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . .206 12-1 cgmxclk frequency for rtc input reference . . . . . . . . . . 219 13-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 13-2 start bit verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 13-3 data bit recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 13-4 stop bit recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 13-5 sci pin functions (standard and infrared). . . . . . . . . . . . . . .250 13-6 character format selection . . . . . . . . . . . . . . . . . . . . . . . . . .253 13-7 sci baud rate prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 13-8 sci baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 13-9 sci baud rate selection examples . . . . . . . . . . . . . . . . . . . . 266 13-10 infrared narrow pulse selection . . . . . . . . . . . . . . . . . . . . . . . 267 14-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 14-2 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 14-3 spi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 14-4 spi master baud rate selection . . . . . . . . . . . . . . . . . . . . . . 298 15-1 mux channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 15-2 adc clock divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 15-3 adc mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 16-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 16-3 lcd bias voltage control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 16-2 resistor ladder selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 16-4 fast charge duty cycle selection . . . . . . . . . . . . . . . . . . . . . 337 16-5 lcd duty cycle selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 16-6 lcd waveform base clock selection . . . . . . . . . . . . . . . . . . 338 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables mc68HC908LJ12 ? rev. 2.0 technical data motorola list of tables 31 table title page 17-1 port control register bits summary. . . . . . . . . . . . . . . . . . . . 343 17-2 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 17-3 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 17-4 port c pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 17-5 port d pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 18-1 irq i/o port register summary . . . . . . . . . . . . . . . . . . . . . . . 359 19-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 21-1 lvi status register (lvisr) . . . . . . . . . . . . . . . . . . . . . . . . . . 381 21-2 lviout bit indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 23-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .392 23-2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 23-3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 23-4 5.0v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 394 23-5 3.3v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 396 23-6 5.0v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 23-7 3.3v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 23-8 5.0v oscillator specifications. . . . . . . . . . . . . . . . . . . . . . . . . 398 23-9 3.3v oscillator specifications. . . . . . . . . . . . . . . . . . . . . . . . . 398 23-10 adc 5.0v electrical characteristics . . . . . . . . . . . . . . . . . . . . 399 23-11 adc 3.3v electrical characteristics . . . . . . . . . . . . . . . . . . . . 400 23-12 flash memory electrical characteristics . . . . . . . . . . . . . . . 406 25-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables technical data mc68HC908LJ12 ? rev. 2.0 32 list of tables motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola general description 33 technical data ? mc68HC908LJ12 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.6.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . 40 1.6.2 analog power supply pin (v dda ) . . . . . . . . . . . . . . . . . . . . . 40 1.6.3 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 41 1.6.4 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.6.5 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.6.6 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . 41 1.6.7 adc voltage high reference pin (v refh ). . . . . . . . . . . . . . 41 1.6.8 adc voltage low reference pin (v refl ) . . . . . . . . . . . . . . 41 1.6.9 port a input/output (i/o) pins (pta7 ? pta0) . . . . . . . . . . . . 42 1.6.10 port b i/o pins (ptb7 ? ptb0) . . . . . . . . . . . . . . . . . . . . . . .42 1.6.11 port c i/o pins (ptc7 ? ptc0) . . . . . . . . . . . . . . . . . . . . . . . 42 1.6.12 port d i/o pins (ptd7 ? ptd0) . . . . . . . . . . . . . . . . . . . . . . . 42 1.6.13 lcd backplane and frontplane (bp0 ? bp2, fp0/bp3, fp1 ? fp18). . . . . . . . . . . . . . . . . .42 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68HC908LJ12 ? rev. 2.0 34 general description motorola 1.2 introduction the mc68HC908LJ12 is a member of the low-cost, high-performance m68hc08 family of 8-bit microcontroller units (mcus). the m68hc08 family is based on the customer-specified integrated circuit (csic) design strategy. all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. 1.3 features features of the mc68HC908LJ12 include the following: high-performance m68hc08 architecture fully upward-compatible object code with m6805, m146805, and m68hc05 families maximum internal bus frequency: ? 8-mhz at 5v operating voltage ? 4-mhz at 3.3v operating voltage 32-khz crystal oscillator clock input with 32mhz internal phase- lock-loop optional continuous crystal oscillator operation in stop mode 12k-bytes user program flash memory with security 1 feature 512 bytes of on-chip ram two 16-bit, 2-channel timer interface modules (tim1 and tim2) with selectable input capture, output compare, and pwm capability on each channel real time clock (rtc) with clock, calendar, alarm, and chronograph functions. selectable periodic interrupt requests for seconds, minutes, hours, days, 2-hz, 4-hz, and 100-hz serial communications interface module (sci) with infrared (ir) encoder/decoder 1. no security feature is absolutely secure. however, motorola ? s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description features mc68HC908LJ12 ? rev. 2.0 technical data motorola general description 35 serial peripheral interface module (spi) irq external interrupt pin with integrated pullup 8-bit keyboard wakeup port with programmable pullup 32 general-purpose input/output (i/o) pins: ? high current 8-ma sink capability on ptb2 ? ptb5 ? high current 20-ma sink capability on ptb0 ? ptb1 4/3 backplanes and static with maximum 27 frontplanes liquid crystal display (lcd) driver 6-channel, 10-bit successive approximation analog-to-digital converter (adc) resident routines for in-circuit programming and eeprom emulation low-power design (fully static with stop and wait modes) master reset pin (with integrated pullup) and power-on reset spike filter protection for emc performance enhancement system protection features ? optional computer operating properly (cop) reset, driven by internal 64-khz rc oscillator ? low-voltage detection with optional reset or interrupt ? illegal opcode detection with reset ? illegal address detection with reset 64-pin quad flat pack (qfp), 64-pin low-profile quad flat pack (lqfp), 52-pin low-profile quad flat pack (lqfp), and die form specific features of the mc68HC908LJ12 in 52-pin lqfp are: ? 20 general-purpose i/os only ? high current 8-ma sink capability on ptb2 ? ptb3 only ? 4-bit keyboard wakeup port with programmable pullup ? no serial peripheral interface module (spi) ? no tim2 input capture/output compare pins ? 4-channel analog-to-digital converter only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68HC908LJ12 ? rev. 2.0 36 general description motorola features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications efficient c language support 1.4 mcu block diagram figure 1-1 shows the structure of the mc68HC908LJ12. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description mcu block diagram mc68HC908LJ12 ? rev. 2.0 technical data motorola general description 37 figure 1-1. mc68HC908LJ12 block diagram system integration module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 96 bytes user flash ? 12,288 bytes user ram ? 512 bytes monitor rom ? 960 bytes user flash vector space ? 48 bytes external interrupt module ddrd portd internal bus * rst * irq computer operating properly module ptd7/kbi7** ptd6/kbi6** ptd5/kbi5** ptd4/kbi4** ptd3/spsck ptd2/mosi power-on reset module power vss vdda ptd1/miso ptd0/ss real time clock module 2-channel timer interface module 1 2-channel timer interface module 2 liquid crystal display driver module serial peripheral interface module keyboard interrupt module 10-bit analog-to-digital converter module clock generator module osc1 osc2 cgmxfc 32.768-khz oscillator phase-locked loop fp0/bp3 vdd adc reference vrefl vrefh ddrb portb ptb7/adc5 ptb6/adc4 ptb5/t2ch1 ? ptb4/t2ch0 ? ptb3/t1ch1 ? ptb2/t1ch0 ? ptb1/rxd ? ptb0/txd ? ddrc portc ptc7/fp26 ptc6/fp25 ptc5/fp24 ptc4/fp23 ptc3/fp22 ptc2/fp21 ptc1/fp20 ptc0/fp19 ddra porta pta7/adc3 pta6/adc2 pta5/adc1 pta4/adc0 pta3/kbi3** pta2/kbi2** pta1/kbi1** pta0/kbi0** low-voltage inhibit module fp1 ? fp18 bp0 ? bp2 * pin contains integrated pullup device. ** pin contains integrated pullup device if configured as kbi. ? high current sink pin, 15ma. ? high current sink pin, 8ma. serial communications interface module (with infrared encoder/decoder) # # # pins available on 64-pin packages only. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68HC908LJ12 ? rev. 2.0 38 general description motorola 1.5 pin assignments figure 1-2. 64-pin qfp and 64-pin lqfp pin assignment fp8 fp6 ptb2/t1ch0 pta4/adc0 fp5 fp4 fp3 fp2 fp1 ptd5/kbi5 fp0/bp3 fp7 ptd6/kbi6 ptd7/kbi7 fp9 fp10 fp11 fp12 vrefl vrefh ptb7/adc5 ptb6/adc4 pta7/adc3 pta6/adc2 pta5/adc1 pta3/kbi3 pta2/kbi2 pta1/kbi1 pta0/kbi0 ptc7/fp26 ptc6/fp25 ptc5/fp24 ptd0/ss ptb1/rxd ptb0/txd cgmxfc osc2 osc1 vss vdd vdda ptd4/kbi4 bp2 bp1 bp0 ptb5/t2ch1 ptb4/t2ch0 ptb3/t1ch1 fp14 ptd3/spsck fp13 fp15 fp16 fp17 fp18 ptc0/fp19 ptd2/mosi ptd1/miso ptc1/fp20 ptc2/fp21 ptc3/fp22 ptc4/fp23 irq rst 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68HC908LJ12 ? rev. 2.0 technical data motorola general description 39 figure 1-3. 52-pin lqfp pin assignment fp9 fp7 cgmxfc pta2/kbi2 fp6 fp5 fp4 fp3 fp2 fp1 fp0/bp3 fp8 fp10 fp11 fp12 vrefl vrefh pta7/adc3 pta6/adc2 pta5/adc1 pta4/adc0 pta3/kbi3 pta1/kbi1 pta0/kbi0 ptc7/fp26 ptc6/fp25 ptc5/fp24 osc2 osc1 vss vdd vdda bp2 bp1 bp0 ptb3/t1ch1 ptb2/t1ch0 ptb1/rxd ptb0/txd fp15 fp13 fp14 fp16 fp17 fp18 ptc0/fp19 ptc1/fp20 ptc2/fp21 ptc3/fp22 ptc4/fp23 irq rst 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 52 51 50 49 48 47 46 45 44 43 42 41 40 pins not available on 52-lqfp package: ptb7adc5 ptd7/kbi7 ptb6/adc4 ptd6/kbi6 ptb5/t2ch1 ptd5/kbi5 ptb4/t2ch0 ptd4/kbi4 ptd3/spsck ptd2/mosi ptd1/miso ptd0/ss internal pads are unconnected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68HC908LJ12 ? rev. 2.0 40 general description motorola 1.6 pin functions description of pin functions are provided here. 1.6.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu as figure 1-4 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response ceramic capacitor for c1. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. v ss must be grounded for proper mcu operation. 1.6.2 analog power supply pin (v dda ) v dda is the voltage supply for the analog parts of the mcu. connect the v dda pin to the same voltage potential as v dd . for maximum noise immunity, route v dda via a separate trace and place bypass capacitors as close as possible to the package (see figure 1-4 ). figure 1-4. power supply bypassing mcu v dd c2(a) c1(a) 0.1 f v ss v dd + note: component values shown represent typical applications. v dda c2(b) c1(b) 0.1 f + v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin functions mc68HC908LJ12 ? rev. 2.0 technical data motorola general description 41 1.6.3 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the connections for the on-chip oscillator circuit. the osc1 pin contains a schmitt-trigger and a spike filter for improved emc performance. see section 7. oscillator (osc) . 1.6.4 external reset pin (rst ) a logic 0 on the rst pin forces the mcu to a known start-up state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. a schmitt-trigger and a spike filter is associated with this pin so that the device is more robust to emc noise.this pin also contains an internal pullup resistor. see section 9. system integration module (sim) . 1.6.5 external interrupt pin (irq ) irq is an asynchronous external interrupt pin. this pin contains an internal pullup resistor. see section 18. external interrupt (irq) . 1.6.6 external filter capacitor pin (cgmxfc) cgmxfc is an external filter capacitor connection for the cgm. see section 8. clock generator module (cgm) . 1.6.7 adc voltage high reference pin (v refh ) v refh is the voltage input pin for the adc voltage high reference. see section 15. analog-to-digital converter (adc) 1.6.8 adc voltage low reference pin (v refl ) v refl is the voltage input pin for the adc voltage low reference. see section 15. analog-to-digital converter (adc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68HC908LJ12 ? rev. 2.0 42 general description motorola 1.6.9 port a input/output (i/o) pins (pta7 ? pta0) pta7 ? pta0 are special function, bidirectional port pins ( section 17. ). pta7/adc3 ? pta4/adc0 are shared with the adc ( section 15. ), and pta3/kbi3 ? pta0/kbi0 are shared with the kbi module ( section 19. ). 1.6.10 port b i/o pins (ptb7 ? ptb0) ptb7 ? ptb0 are special function, bidirectional port pins ( section 17. ). ptb0/txd ? ptb1/rxd are shared with the sci module ( section 13. ), ptb5/t2ch1 ? ptb4/t2ch0 are shared with the tim2 ( section 11. ), ptb3/t1ch1 ? ptb2/t1ch0 are shared with the tim1( section 11. ), ptb6/adc4 ? ptb7/adc5 are shared with the adc ( section 15. ). 1.6.11 port c i/o pins (ptc7 ? ptc0) ptc7 ? ptc0 are special function, bidirectional port pins ( section 17. ). ptc7/fp26 ? ptc0/fp19 are shared with the lcd frontplane drivers ( section 16. ). 1.6.12 port d i/o pins (ptd7 ? ptd0) ptd7 ? ptd0 are special function, bidirectional port pins ( section 17. ). ptd7/kbi7 ? ptd4/kbi4 are shared with kbi module ( section 19. ). ptd3/spsck ? ptd0/ss are shared with spi module ( section 14. ). 1.6.13 lcd backplane and frontplane (bp0 ? bp2, fp0/bp3, fp1 ? fp18) bp0 ? bp2 are the lcd backplane driver pins and fp1 ? fp18 are the frontplane driver pins. fp0/bp3 is the shared driver pin between fp0 and bp3 ( section 16. ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola memory map 43 technical data ? mc68HC908LJ12 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . .43 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . .44 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 2.2 introduction the cpu08 can address 64k-bytes of memory space. the memory map, shown in figure 2-1 , includes: 12,288 bytes of user flash memory 512 bytes of random-access memory (ram) 48 bytes of user-defined vectors 960 bytes of monitor rom 2.3 unimplemented memory locations accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68HC908LJ12 ? rev. 2.0 44 memory map motorola 2.4 reserved memory locations accessing a reserved location can have unpredictable effects on mcu operation. in the figure 2-1 and in register figures in this document, reserved locations are marked with the word reserved or with the letter r. 2.5 input/output (i/o) section most of the control, status, and data registers are in the zero page area of $0000 ? $005f. additional i/o registers have these addresses: $fe00; sim break status register, sbsr $fe01; sim reset status register, srsr $fe02; reserved $fe03; sim break flag control register, sbfcr $fe04; interrupt status register 1, int1 $fe05; interrupt status register 2, int2 $fe06; interrupt status register 3, int3 $fe07; reserved $fe08; flash control register, flcr $fe09; flash block protect register, flbpr $fe0a; reserved $fe0b; reserved $fe0c; break address register high, brkh $fe0d; break address register low, brkl $fe0e; break status and control register, brkscr $fe0f; lvi status register, lvisr $ffff; cop control register, copctl data registers are shown in figure 2-2 . table 2-1 is a list of vector locations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908LJ12 ? rev. 2.0 technical data motorola memory map 45 $0000 $005f i/o registers 96 bytes $0060 $025f ram 512 bytes $0260 $bfff unimplemented 48,544 bytes $c000 $efff flash memory 12,288 bytes $f000 $fbff unimplemented 3,072 bytes $fc00 $fdff monitor rom 1 512 bytes $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 interrupt status register 3 (int3) $fe07 reserved $fe08 flash control register (flcr) $fe09 flash block protect register (flbpr) $fe0a reserved $fe0b reserved $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and control register (brkscr) $fe0f lvi status register (lvisr) $fe10 $ffcf monitor rom 2 448 bytes $ffd0 $ffff flash vectors 48 bytes figure 2-1. memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68HC908LJ12 ? rev. 2.0 46 memory map motorola addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset:uuuuuuuu $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset:uuuuuuuu $0002 port c data register (ptc) read: ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset:uuuuuuuu $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset:uuuuuuuu $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 unimplemented read: write: reset: $0009 unimplemented read: write: reset: u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 1 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908LJ12 ? rev. 2.0 technical data motorola memory map 47 $000a unimplemented read: write: reset: $000b unimplemented read: write: reset: $000c port b led control register (ledb) read: 0 0 ledb5 ledb4 ledb3 ledb2 ledb1 ledb0 write: reset:00000000 $000d unimplemented read: write: reset: $000e unimplemented read: write: reset: $000f unimplemented read: write: reset: $0010 spi control register (spcr) read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0011 spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $0012 spi data register (spdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:uuuuuuuu $0013 sci control register 1 (scc1) read: loops ensci 0 mwakeiltypenpty write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 2 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68HC908LJ12 ? rev. 2.0 48 memory map motorola $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset: uu 000000 $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 sci status register 2 (scs2) read: 000000bkfrpf write: reset:00000000 $0018 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: uuuuuuuu $0019 sci baud rate register (scbr) read: cks 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 $001a sci infrared control register (scircr) read: r 000 r tnp1 tnp0 iren write: reset:00000000 $001b keyboard status and control register (kbscr) read: 0000keyf0 imaskk modek write: ackk reset:00000000 $001c keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $001d configuration register 2 (config2) ? read: 0 stop_ ircdis stop_ xclken div2clk pceh pcel lvisel1 lvisel0 write: reset:0000000 ?? 0 ?? addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 3 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908LJ12 ? rev. 2.0 technical data motorola memory map 49 $001e irq status and control register (intscr) read: 0000irqf0 imask mode write: ack reset:00000000 $001f configuration register 1 (config1) ? read: coprs lvistop lvirstd lvipwrd 0 ssrec stop copd write: reset:00010000 ? one-time writable register after each reset. ?? reset by por only. $0020 timer 1 status and control register (t1sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer 1 counter register high (t1cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 timer 1 counter register low (t1cntl) read: bit 7 654321bit 0 write: reset:00000000 $0023 timer 1 counter modulo register high (t1modh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0024 timer 1 counter modulo register low (t1modl) read: bit 7654321bit 0 write: reset:11111111 $0025 timer 1 channel 0 status and control register (t1sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 timer 1 channel 0 register high (t1ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:xxxxxxxx addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 4 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68HC908LJ12 ? rev. 2.0 50 memory map motorola $0027 timer 1 channel 0 register low (t1ch0l) read: bit 7654321bit 0 write: reset:xxxxxxxx $0028 timer 1 channel 1 status and control register (t1sc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 timer 1 channel 1 register high (t1ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:xxxxxxxx $002a timer 1 channel 1 register low (t1ch1l) read: bit 7654321bit 0 write: reset:xxxxxxxx $002b timer 2 status and control register (t2sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $002c timer 2 counter register high (t2cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $002d timer 2 counter register low (t2cntl) read: bit 7 654321bit 0 write: reset:00000000 $002e timer 2 counter modulo register high (t2modh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $002f timer 2 counter modulo register low (t2modl) read: bit 7654321bit 0 write: reset:11111111 $0030 timer 2 channel 0 status and control register (t2sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 5 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908LJ12 ? rev. 2.0 technical data motorola memory map 51 $0031 timer 2 channel 0 register high (t2ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:xxxxxxxx $0032 timer 2 channel 0 register low (t2ch0l) read: bit 7654321bit 0 write: reset:xxxxxxxx $0033 timer 2 channel 1 status and control register (t2sc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0034 timer 2 channel 1 register high (t2ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:xxxxxxxx $0035 timer 2 channel 1 register low (t2ch1l) read: bit 7654321bit 0 write: reset:xxxxxxxx $0036 pll control register (ptcl) read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00100000 $0037 pll bandwidth control register (pbwc) read: auto lock acq 0000 r write: reset:00000000 $0038 pll multiplier select register high (pmsh) read: 0000 mul11 mul10 mul9 mul8 write: reset:00000000 $0039 pll multiplier select register low (pmsl) read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 $003a pll vco range select register (pmrs) read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 6 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68HC908LJ12 ? rev. 2.0 52 memory map motorola $003b pll reference divider select register (pmds) read: 0000 rds3 rds2 rds1 rds0 write: reset: 0 00 0 0001 $003c adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $003d adc data register high (adrh) read: adx adx adx adx adx adx adx adx write:rrrrrrrr reset:00000000 $003e adc data register low (adrl) read: adx adx adx adx adx adx adx adx write:rrrrrrrr reset:00000000 $003f adc clock register (adclk) read: adiv2 adiv1 adiv0 adiclk mode1 mode0 00 write: r reset:00000100 $0040 unimplemented read: write: reset: $0041 unimplemented read: write: reset: $0042 rtc control register 1 (rtccr1) read: almie chrie dayie hrie minie secie tb1ie tb2ie write: reset:00000000 $0043 rtc control register 2 (rtccr2) read: 0 0 chre rtce 0 xtl2 xtl1 xtl0 write: r chrclr reset:00000000 $0044 rtc status register (rtcsr) read: almf chrf dayf hrf minf secf tb1f tb2f write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 7 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908LJ12 ? rev. 2.0 technical data motorola memory map 53 $0045 alarm minute register (almr) read: 00 am5 am4 am3 am2 am1 am0 write: reset:00000000 $0046 alarm hour register (alhr) read: 000 ah4 ah3 ah2 ah1 ah0 write: reset:00000000 $0047 second register (secr) read: 0 0 sec5 sec4 sec3 sec2 sec1 sec0 write: reset:00000000 $0048 minute register (minr) read: 0 0 min5 min4 min3 min2 min1 min0 write: reset:00000000 $0049 hour register (hrr) read: 0 0 0 hr4 hr3 hr2 hr1 hr0 write: reset:00000000 $004a day register (dayr) read: 0 0 0 day4 day3 day2 day1 day0 write: reset:00000001 $004b month register (mthr) read: 0000 mth3 mth2 mth1 mth0 write: reset:00000001 $004c year register (yrr) read: yr7 yr6 yr5 yr4 yr3 yr2 yr1 yr0 write: reset:00000000 $004d day-of-week register (dowr) read: 00000 dow2 dow1 dow0 write: reset:00000000 $004e chronograph data register (chrr) read: 0 chr6 chr5 chr4 chr3 chr2 chr1 chr0 write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 8 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68HC908LJ12 ? rev. 2.0 54 memory map motorola $004f lcd clock register (lcdclk) read: 0 fcctl1 fcctl0 duty1 duty0 lclk2 lclk1 lclk0 write: reset:00000000 $0050 reserved read: rrrrrrrr write: reset: $0051 lcd control register (lcdcr) read: lcde 0 fc lc lccon3 lccon2 lccon1 lccon0 write: reset:00000000 $0052 lcd data register 1 (ldat1) read: f1b3 f1b2 f1b1 f1b0 f0b3 f0b2 f0b1 f0b0 write: reset:uuuuuuuu $0053 lcd data register 2 (ldat2) read: f3b3 f3b2 f3b1 f3b0 f2b3 f2b2 f2b1 f2b0 write: reset:uuuuuuuu $0054 lcd data register 3 (ldat3) read: f5b3 f5b2 f5b1 f5b0 f4b3 f4b2 f4b1 f4b0 write: reset:uuuuuuuu $0055 lcd data register 4 (ldat4) read: f7b3 f7b2 f7b1 f7b0 f6b3 f6b2 f6b1 f6b0 write: reset:uuuuuuuu $0056 lcd data register 5 (ldat5) read: f9b3 f9b2 f9b1 f9b0 f8b3 f8b2 f8b1 f8b0 write: reset:uuuuuuuu $0057 lcd data register 6 (ldat6) read: f11b3 f11b2 f11b1 f11b0 f10b3 f10b2 f10b1 f10b0 write: reset:uuuuuuuu $0058 lcd data register 7 (ldat7) read: f13b3 f13b2 f13b1 f13b0 f12b3 f12b2 f12b1 f12b0 write: reset:uuuuuuuu addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 9 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908LJ12 ? rev. 2.0 technical data motorola memory map 55 $0059 lcd data register 8 (ldat8) read: f15b3 f15b2 f15b1 f15b0 f14b3 f14b2 f14b1 f14b0 write: reset:uuuuuuuu $005a lcd data register 9 (ldat9) read: f17b3 f17b2 f17b1 f17b0 f16b3 f16b2 f16b1 f16b0 write: reset:uuuuuuuu $005b lcd data register 10 (ldat10) read: f19b3 f19b2 f19b1 f19b0 f18b3 f18b2 f18b1 f18b0 write: reset:uuuuuuuu $005c lcd data register 11 (ldat11) read: f21b3 f21b2 f21b1 f21b0 f20b3 f20b2 f20b1 f20b0 write: reset:uuuuuuuu $005d lcd data register 12 (ldat12) read: f23b3 f23b2 f23b1 f23b0 f22b3 f22b2 f22b1 f22b0 write: reset:uuuuuuuu $005e lcd data register 13 (ldat13) read: f25b3 f25b2 f25b1 f25b0 f24b3 f24b2 f24b1 f24b0 write: reset:uuuuuuuu $005f lcd data register 14 (ldat14) read: f26b3 f26b2 f26b1 f26b0 write: reset:uuuuuuuu $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 10 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68HC908LJ12 ? rev. 2.0 56 memory map motorola $fe02 reserved read: rrrrrrrr write: reset: $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) read: 00000if17if16if15 write:rrrrrrrr reset:00000000 $fe07 reserved read: rrrrrrrr write: reset: $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe09 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 $fe0a reserved read: rrrrrrrr write: reset: $fe0b reserved read: rrrrrrrr write: reset: addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 11 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908LJ12 ? rev. 2.0 technical data motorola memory map 57 $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 $fe0f low-voltage inhibit status register (lvisr) read: lviout lviie lviif00000 write: lviiak reset:00000000 $ffff cop control register (copctl) read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 12 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68HC908LJ12 ? rev. 2.0 58 memory map motorola . table 2-1. vector addresses priority int flag address vector lowest highest if17 $ffda real time clock vector (high) $ffdb real time clock vector (low) if16 $ffdc adc conversion complete vector (high) $ffdd adc conversion complete vector (low) if15 $ffde keyboard vector (high) $ffdf keyboard vector (low) if14 $ffe0 sci transmit vector (high) $ffe1 sci transmit vector (low) if13 $ffe2 sci receive vector (high) $ffe3 sci receive vector (low) if12 $ffe4 sci error vector (high) $ffe5 sci error vector (low) if11 $ffe6 spi receive vector (high) $ffe7 spi receive vector (low) if10 $ffe8 spi transmit vector (high) $ffe9 spi transmit vector (low) if9 $ffea tim2 overflow vector (high) $ffeb tim2 overflow vector (low) if8 $ffec tim2 channel 1 vector (high) $ffed tim2 channel 1 vector (low) if7 $ffee tim2 channel 0 vector (high) $ffef tim2 channel 0 vector (low) if6 $fff0 tim1 overflow vector (high) $fff1 tim1 overflow vector (low) if5 $fff2 tim1 channel 1 vector (high) $fff3 tim1 channel 1 vector (low) if4 $fff4 tim1 channel 0 vector (high) $fff5 tim1 channel 0 vector (low) if3 $fff6 pll vector (high) $fff7 pll vector (low) if2 $fff8 lvi vector (high) $fff9 lvi vector (low) if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) $ffff reset vector (low) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola random-access memory (ram) 59 technical data ? mc68HC908LJ12 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.2 introduction this section describes the 512 bytes of ram (random-access memory). 3.3 functional description addresses $0060 through $025f are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64k-byte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 160 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff out of page zero, direct addressing mode instructions can efficiently access all page zero ram locations. page zero ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . random-access memory (ram) technical data mc68HC908LJ12 ? rev. 2.0 60 random-access memory (ram) motorola during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola flash memory (flash) 61 technical data ? mc68HC908LJ12 section 4. flash memory (flash) 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 4.5 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.8.1 flash block protect register . . . . . . . . . . . . . . . . . . . . . . .68 4.2 introduction this section describes the operation of the embedded flash memory. this memory can be read, programmed, and erased from a single external supply. the program and erase operations are enabled through the use of an internal charge pump. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) technical data mc68HC908LJ12 ? rev. 2.0 62 flash memory (flash) motorola 4.3 functional description the flash memory consists of an array of 12,288 bytes for user memory plus a block of 48 bytes for user interrupt vectors. an erased bit reads as logic 1 and a programmed bit reads as a logic 0 . the flash memory page size is defined as 128 bytes, and is the minimum size that can be erased in a page erase operation. program and erase operations are facilitated through control bits in flash control register (flcr). the address ranges for the flash memory are: $c000 ? $efff; user memory; 12,288 bytes $ffd0 ? $ffff; user interrupt vectors; 48 bytes programming tools are available from motorola. contact your local motorola representative for more information. note: a security feature prevents viewing of the flash contents. 1 addr.register name bit 7654321bit 0 $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe09 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 = unimplemented figure 4-1. flash i/o register summary 1. no security feature is absolutely secure. however, motorola ? s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) flash control register mc68HC908LJ12 ? rev. 2.0 technical data motorola flash memory (flash) 63 4.4 flash control register the flash control register (flcr) controls flash program and erase operations. hven ? high voltage enable bit this read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. hven can only be set if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit this read/write bit configures the memory for mass erase operation or block erase operation when the erase bit is set. 1 = mass erase operation selected 0 = block erase operation selected erase ? erase control bit this read/write bit configures the memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation not selected pgm ? program control bit this read/write bit configures the memory for program operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation not selected address: $fe08 bit 7654321bit 0 read: 0000 hven mass erase pgm write: reset:00000000 figure 4-2. flash control register (flcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) technical data mc68HC908LJ12 ? rev. 2.0 64 flash memory (flash) motorola 4.5 flash page erase operation use the following procedure to erase a page of flash memory. a page consists of 128 consecutive bytes starting from addresses $xx00 or $xx80. the 48-byte user interrupt vectors area also forms a page. the 48-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. mass erase is required to erase this page. 1. set the erase bit and clear the mass bit in the flash control register. 2. write any data to any flash address within the page address range desired. 3. wait for a time, t nvs (at least 10 s). 4. set the hven bit. 5. wait for a time, t erase (1ms). 6. clear the erase bit. 7. wait for a time, t nvh (5 s). 8. clear the hven bit. 9. after time, t rcv (1 s), the memory can be accessed again in read mode. note: programming and erasing of flash locations cannot be performed by executing code from the flash memory; the code must be executed from ram. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) flash mass erase operation mc68HC908LJ12 ? rev. 2.0 technical data motorola flash memory (flash) 65 4.6 flash mass erase operation use the following procedure to erase the entire flash memory to read as logic 1: 1. set both the erase bit and the mass bit in the flash control register. 2. write any data to any flash address within the flash memory address range. 3. wait for a time, t nvs (10 s). 4. set the hven bit. 5. wait for a time t merase (4ms). 6. clear the erase bit. 7. wait for a time, t nvhl (100 s). 8. clear the hven bit. 9. after time, t rcv (1 s), the memory can be accessed again in read mode. note: programming and erasing of flash locations cannot be performed by executing code from the flash memory; the code must be executed from ram. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) technical data mc68HC908LJ12 ? rev. 2.0 66 flash memory (flash) motorola 4.7 flash program operation programming of the flash memory is done on a row basis. a row consists of 64 consecutive bytes starting from addresses $xx00, $xx40, $xx80, or $xxc0. the procedure for programming a row of the flash memory is outlined below: 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. write any data to any flash address within the row address range desired. 3. wait for a time, t nvs (10 s). 4. set the hven bit. 5. wait for a time, t pgs (5 s). 6. write data to the flash address to be programmed. 7. wait for time, t prog (30 s). 8. repeat step 6 and 7 until all the bytes within the row are programmed. 9. clear the pgm bit. 10. wait for time, t nvh (5 s). 11. clear the hven bit. 12. after time, t rcv (1 s), the memory can be accessed again in read mode. this program sequence is repeated throughout the memory until all data is programmed. note: programming and erasing of flash locations cannot be performed by executing code from the flash memory; the code must be executed from ram. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. do not exceed t prog maximum. see 23.18 flash memory characteristics . figure 4-3 shows a flowchart representation for programming the flash memory. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) flash program operation mc68HC908LJ12 ? rev. 2.0 technical data motorola flash memory (flash) 67 figure 4-3. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 6 to step 6), or must not exceed the maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 6 to step 9) note: 1 2 3 4 5 6 7 9 10 11 12 algorithm for programming a row (64 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) technical data mc68HC908LJ12 ? rev. 2.0 68 flash memory (flash) motorola 4.8 flash protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made to protect pages of memory from unintentional erase or program operations due to system malfunction. this protection is done by use of a flash block protect register (flbpr). the flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a location defined by flbpr and ends to the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or program operations. note: when the flbpr is cleared (all 0 ? s), the entire flash memory is protected from being programmed and erased. when all the bits are set, the entire flash memory is accessible for program and erase. 4.8.1 flash block protect register the flash block protect register is implemented as an 8-bit i/o register. the content of this register determine the starting location of the protected range within the flash memory. bpr[7:0] ? flash block protect register bit 7 to bit 0 bpr[7:1] represent bits [13:7] of a 16-bit memory address. bits [15:14] are logic 1 ? s and bits [6:0] are logic 0 ? s. figure 4-5. flash block protect start address address: $fe09 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 figure 4-4. flash block protect register (flbpr) 16-bit memory address start address of flash block protect 11 0000000 bpr[7:1] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) flash protection mc68HC908LJ12 ? rev. 2.0 technical data motorola flash memory (flash) 69 bpr0 is used only for bpr[7:0] = $ff, for no block protection. the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. the flash is protected from this start address to the end of flash memory, at $ffff. with this mechanism, the protect start address can be xx00 or xx80 (at page boundaries ? 128 bytes) within the flash memory. examples of protect start address: bpr[7:0] start of address of protect range $00 or $01 $c000 (11 00 0000 0 000 0000) the entire flash memory is protected. $02 or $03 $c080 (11 00 0000 1 000 0000) $04 or $05 $c100 (11 00 0001 0 000 0000) $06 or $07 $c180 (11 00 0001 1 000 0000) $08 or $09 $c200 (11 00 0010 0 000 0000) and so on... $f8 or $f9 $fe00 (11 11 1110 0 000 0000) $fa or $fb $fe80 (11 11 1110 1 000 0000) $fc or $fd $ff00 (11 11 1111 0 000 0000) $fe $ff80 (11 11 1111 1 000 0000) $ff the entire flash memory is not protected. note: the end address of the protected range is always $ffff. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) technical data mc68HC908LJ12 ? rev. 2.0 70 flash memory (flash) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola configuration registers (config) 71 technical data ? mc68HC908LJ12 section 5. configuration registers (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.4 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . .73 5.5 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . . .75 5.2 introduction this section describes the configuration registers, config1 and config2. the configuration registers enable or disable these options: computer operating properly module (cop) cop timeout period (2 18 ? 2 4 or 2 13 ? 2 4 iclk cycles) low-voltage inhibit (lvi) module power lvi module reset lvi module in stop mode lvi module voltage trip point selection stop instruction stop mode recovery time (32 iclk cycles or 4096 iclk cycles) oscillator during stop mode lcd frontplanes fp19 ? fp26 on port c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration registers (config) technical data mc68HC908LJ12 ? rev. 2.0 72 configuration registers (config) motorola 5.3 functional description the configuration registers are used in the initialization of various options. the configuration registers can be written once after each reset. all of the configuration register bits are cleared during reset. since the various options affect the operation of the mcu, it is recommended that these registers be written immediately after reset. the configuration registers are located at $001d and $001f. the configuration registers may be read at anytime. note: the options except lvisel[1:0] are one-time writable by the user after each reset. the lvisel[1:0] bits are one-time writable by the user only after each por (power-on reset). the config registers are not in the flash memory but are special registers containing one-time writable latches after each reset. upon a reset, the config registers default to predetermined settings as shown in figure 5-2 and figure 5-3 . addr.register name bit 7654321bit 0 $001d configuration register 2 (config2) ? read: 0 stop_ ircdis stop_ xclken div2clk pceh pcel lvisel1 lvisel0 write: reset:0000000 ?? 0 ?? $001f configuration register 1 (config1) ? read: coprs lvistop lvirstd lvipwrd 0 ssrec stop copd write: reset:00010000 ? one-time writable register after each reset. ?? reset by por only. = unimplemented figure 5-1. config registers summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration registers (config) configuration register 1 (config1) mc68HC908LJ12 ? rev. 2.0 technical data motorola configuration registers (config) 73 5.4 configuration register 1 (config1) coprs ? cop rate select coprs selects the cop time-out period. reset clears coprs. (see section 20. computer operating properly (cop) .) 1 = cop time out period = 2 13 ? 2 4 iclk cycles 0 = cop time out period = 2 18 ? 2 4 iclk cycles lvistop ? lvi enable in stop mode when the lvipwrd bit is clear, setting the lvistop bit enables the lvi to operate during stop mode. reset clears lvistop. (see section 21. low-voltage inhibit (lvi) .) 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode lvirstd ? lvi reset disable lvirstd disables the reset signal from the lvi module. (see section 21. low-voltage inhibit (lvi) .) 1 = lvi module resets disabled 0 = lvi module resets enabled lvipwrd ? lvi power disable bit lvipwrd disables the lvi module. (see section 21. low-voltage inhibit (lvi) .) reset sets lvipwrd. 1 = lvi module power disabled 0 = lvi module power enabled address: $001f bit 7654321bit 0 read: coprs lvistop lvirstd lvipwrd 0 ssrec stop copd write: reset:00010000 = unimplemented figure 5-2. configuration register 1 (config1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration registers (config) technical data mc68HC908LJ12 ? rev. 2.0 74 configuration registers (config) motorola ssrec ? short stop recovery ssrec enables the cpu to exit stop mode with a delay of 32 iclk cycles instead of a 4096 iclk cycle delay. 1 = stop mode recovery after 32 iclk cycles 0 = stop mode recovery after 4096 iclk cycles note: exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal oscillator, do not set the ssrec bit. note: when the lvistop is enabled, the system stabilization time for power on reset and long stop recovery (both 4096 iclk cycles) gives a delay longer than the enable time for the lvi. there is no period where the mcu is not protected from a low power condition. however, when using the short stop recovery configuration option, the 32 iclk delay is less than the lvi ? s turn-on time and there exists a period in start-up where the lvi is not protecting the mcu. stop ? stop instruction enable stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. (see section 20. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration registers (config) configuration register 2 (config2) mc68HC908LJ12 ? rev. 2.0 technical data motorola configuration registers (config) 75 5.5 configuration register 2 (config2) stop_ircdis ? internal rc oscillator stop mode disable setting stop_ircdis disables the internal rc oscillator during stop mode. when this bit is cleared, the internal rc oscillator continues to operate in stop mode. reset clears this bit. 1 = internal rc oscillator disabled during stop mode 0 = internal rc oscillator enabled during stop mode stop_xclken ? crystal oscillator stop mode enable setting stop_xclken enables the external crystal (xtal) oscillator to continue operating during stop mode. this is useful for driving the real time clock module to allow it to generate periodic wake-up while in stop mode. when this bit is cleared, the external xtal oscillator will be disabled during stop mode. reset clears this bit. 1 = xtal oscillator enabled during stop mode 0 = xtal oscillator disabled during stop mode div2clk ? divide-by-2 clock bypass when cgmxclk is selected to drive the system clocks (bcs=0), setting div2clk allows the cgmxclk to bypass the divide-by-2 divider in the cgm module; cgmout will equal cgmxclk and bus clock will equal cgmxclk divide-by-2. div2clk bit has no effect when the bcs=1 in the pll control register (cgmvclk selected and divide-by-2 always enabled). reset clears this bit. 1 = divide-by-2 divider bypassed; when bsc=0, cgmout equals cgmxclk 0 = divide-by-2 divider enabled; when bsc=0, cgmout equals cgmxclk divide-by-2 address: $001d bit 7654321bit 0 read: 0 stop_ ircdis stop_ xclken div2clk pceh pcel lvisel1 lvisel0 write: reset:0000000 ?? 0 ?? = unimplemented ?? reset by por only. figure 5-3. configuration register 2 (config2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration registers (config) technical data mc68HC908LJ12 ? rev. 2.0 76 configuration registers (config) motorola pceh ? port c enable high nibble setting pceh configures the ptc4/fp23 ? ptc7/fp26 pins for lcd frontplane driver use. reset clears this bit. 1 = ptc4/fp23 ? ptc7/fp26 pins configured as lcd frontplane driver pins: fp23 ? fp26 0 = ptc4/fp23 ? ptc7/fp26 pins configured as standard i/o pins: ptc4 ? ptc7 pcel ? port c enable low nibble setting pcel configures the ptc0/fp19 ? ptc3/fp22 pins for lcd frontplane driver use. reset clears this bit. 1 = ptc0/fp19 ? ptc3/fp22 pins configured as lcd frontplane driver pins: fp19 ? fp22 0 = ptc0/fp19 ? ptc3/fp22 pins configured as standard i/o pins: ptc0 ? ptc3 lvisel[1:0] ? lvi operating mode selection lvisel[1:0] selects the voltage operating mode of the lvi module. (see section 21. low-voltage inhibit (lvi) .) the voltage mode selected for the lvi should match the operating v dd . see section 23. electrical specifications for the lvi voltage trip points for each of the modes. lvisel1 lvisel0 operating mode 0 0 reserved (2.5v) 01 3v 10 5v 11 reserved table 5-1. lvi trip point selection f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola central processor unit (cpu) 77 technical data ? mc68HC908LJ12 section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .82 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . .84 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 6.7 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68HC908LJ12 ? rev. 2.0 78 central processor unit (cpu) motorola 6.2 introduction the m68hc08 cpu (central processor unit) is an enhanced and fully object-code-compatible version of the m68hc05 cpu. the cpu08 reference manual (motorola document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 6.3 features feature of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64-kbytes low-power stop and wait modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68HC908LJ12 ? rev. 2.0 technical data motorola central processor unit (cpu) 79 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu registers are not part of the memory map. figure 6-1. cpu registers 6.4.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two ? s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68HC908LJ12 ? rev. 2.0 80 central processor unit (cpu) motorola 6.4.2 index register the 16-bit index register allows indexed addressing of a 64k-byte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, the cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. 6.4.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x) bit 15 1413121110987654321 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68HC908LJ12 ? rev. 2.0 technical data motorola central processor unit (cpu) 81 note: the location of the stack is arbitrary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 6.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. program counter (pc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68HC908LJ12 ? rev. 2.0 82 central processor unit (cpu) motorola 6.4.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to logic 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add- with-carry (adc) operation. the half-carry flag is required for binary- coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 7654321bit 0 read: v11hinzc write: reset: x11x1xxx x = indeterminate figure 6-6. condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68HC908LJ12 ? rev. 2.0 technical data motorola central processor unit (cpu) 83 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68HC908LJ12 ? rev. 2.0 84 central processor unit (cpu) motorola c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.5 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (motorola document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 6.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.6.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu during break interrupts mc68HC908LJ12 ? rev. 2.0 technical data motorola central processor unit (cpu) 85 6.6.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the condition code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock. after exiting stop mode, the cpu clock begins running after the oscillator stabilization delay. 6.7 cpu during break interrupts if the break module is enabled, a break interrupt causes the cpu to execute the software interrupt instruction (swi) at the completion of the current cpu instruction. (see section 22. break module (brk) .) the program counter vectors to $fffc ? $fffd ($fefc ? $fefd in monitor mode). a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. 6.8 instruction set summary table 6-1 provides a summary of the m68hc08 instruction set. 6.9 opcode map the opcode map is provided in table 6-2 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68HC908LJ12 ? rev. 2.0 86 central processor unit (cpu) motorola table 6-1. instruction set summary (sheet 1 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ?????? imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ?????? imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ? ?? ??? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ?????? rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68HC908LJ12 ? rev. 2.0 technical data motorola central processor unit (cpu) 87 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ?????? rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ?????? rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v) = 0 ?????? rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v) = 0 ?????? rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ?????? rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ?????? rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ?????? rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ?????? rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ?????? rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ?????? rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ?????? rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ?????? rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ?????? rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ?????? rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ?????? rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ?????? rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ?????? rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ?????? rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ?????? rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ?????? rel 20 rr 3 table 6-1. instruction set summary (sheet 2 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68HC908LJ12 ? rev. 2.0 88 central processor unit (cpu) motorola brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ?????? rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ?????? rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ????? 0inh 98 1 cli clear interrupt mask i 0 ?? 0 ??? inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0 ?? 01 ? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 6-1. instruction set summary (sheet 3 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68HC908LJ12 ? rev. 2.0 technical data motorola central processor unit (cpu) 89 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one ? s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0 ?? ?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ? ?? ??? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u ?? ??? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? ?? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0 ?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction set summary (sheet 4 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68HC908LJ12 ? rev. 2.0 90 central processor unit (cpu) motorola inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0 ?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0 ?? ?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0 ?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ? ?? 0 ?? dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 table 6-1. instruction set summary (sheet 5 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68HC908LJ12 ? rev. 2.0 technical data motorola central processor unit (cpu) 91 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0 ?? ?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ? 0 ??? 0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two ? s complement) m ? (m) = $00 ? (m) a ? (a) = $00 ? (a) x ? (x) = $00 ? (x) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) ? ?? ??? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ?????? inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ?????? inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ?????? inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ?????? inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ?????? inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ?????? inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ?????? inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ?????? inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ? ?? ??? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ? ?? ??? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ?????? inh 9c 1 table 6-1. instruction set summary (sheet 6 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68HC908LJ12 ? rev. 2.0 92 central processor unit (cpu) motorola rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ?????? inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ?????? inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ????? 1inh 99 1 sei set interrupt mask i 1 ?? 1 ??? inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0 ?? ?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ?? ?? ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ?? 0 ??? inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0 ?? ?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction set summary (sheet 7 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68HC908LJ12 ? rev. 2.0 technical data motorola central processor unit (cpu) 93 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ?? 1 ??? inh 83 9 tap transfer a to ccr ccr (a) ?????? inh 84 2 tax transfer a to x x (a) ?????? inh 97 1 tpa transfer ccr to a a (ccr) ?????? inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ?? ?? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ?????? inh 95 2 txa transfer x to a a (x) ?????? inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ?????? inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressing mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ( ) negation (two ? s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location ? set or cleared n negative bit ? not affected table 6-1. instruction set summary (sheet 8 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68HC908LJ12 ? rev. 2.0 94 central processor unit (cpu) motorola table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789 abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3 ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3 ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3 ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3 ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 tap 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3 ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3 ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3 ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 tax 1inh 2 ais 2imm 3 sta 2dir 4 sta 3 ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3 ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3 ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3 ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3 ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3 ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3 ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3 ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3 ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola oscillator (osc) 95 technical data ? mc68HC908LJ12 section 7. oscillator (osc) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.3 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.4 crystal (x-tal) oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 98 7.5.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . 98 7.5.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 98 7.5.4 internal rc clock (iclk) . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.5.5 cgm oscillator clock (cgmxclk) . . . . . . . . . . . . . . . . . . . 98 7.5.6 cgm reference clock (cgmrclk) . . . . . . . . . . . . . . . . . . 98 7.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.7 oscillator during break mode. . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.2 introduction the oscillator module provides the reference clock for the clock generator module (cgm), the real time clock module (rtc), and other mcu sub-systems. the oscillator module consist of two types of oscillator circuits: internal rc oscillator crystal (x-tal) oscillator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) technical data mc68HC908LJ12 ? rev. 2.0 96 oscillator (osc) motorola the reference clock for the cgm, real time clock module (rtc), and other mcu sub-systems is driven by the crystal oscillator. the cop module is always driven by internal rc oscillator. the rc internal oscillator runs continuously after a por or reset and is always available in run and wait modes. in stop mode, it can be disabled by setting the stop_ircdis bit in config2 register. figure 7-1 . shows the block diagram of the oscillator module. figure 7-1. oscillator module block diagram c 1 c 2 r b x 1 r s * *r s can be zero (shorted) when used with higher-frequency crystals. mcu refer to manufacturer ? s data. osc2 osc1 see section 23. for component value requirements. stop_xclken config2 cgmxclk to rtc, adc, lcd, internal rc en simoscen stop_ircdis config2 iclk from sim to sim, cop cgmrclk cgm clock selection mux oscillator to cgm pll crystal oscillator internal rc oscillator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) internal oscillator mc68HC908LJ12 ? rev. 2.0 technical data motorola oscillator (osc) 97 7.3 internal oscillator the internal rc oscillator clock (iclk) is a free running 64khz clock (at v dd = 5v) that requires no external components. it is the reference clock input to the computer operating properly (cop) module. the iclk can be turned off in stop mode by setting the stop_ircdis bit in config2. after reset, the bit is clear by default and iclk is enabled during stop mode. 7.4 crystal (x-tal) oscillator the crystal (x-tal) oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an accurate clock source. in its typical configuration, the x-tal oscillator is connected in a pierce oscillator configuration, as shown in figure 7-1 . this figure shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. refer to the crystal manufacturer ? s data for more information. 7.5 i/o signals the following paragraphs describe the oscillator i/o signals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) technical data mc68HC908LJ12 ? rev. 2.0 98 oscillator (osc) motorola 7.5.1 crystal amplifier input pin (osc1) osc1 pin is an input to the crystal oscillator amplifier. schmitt trigger and glitch filter are implemented on this pin to improve emc performance. see section 23. electrical specifications for detail specification of the glitch filter. 7.5.2 crystal amplifier output pin (osc2) osc2 pin is the output of the crystal oscillator inverting amplifier. 7.5.3 oscillator enable signal (simoscen) the simoscen signal from the system integration module (sim) enables/disables the internal rc and x-tal oscillator circuits. 7.5.4 internal rc clock (iclk) the iclk clock is the output from the internal rc oscillator. this clock drives the sim and cop modules. 7.5.5 cgm oscillator clock (cgmxclk) the cgmxclk clock is the output from the x-tal oscillator. this clock drives to cgm, real time clock module, analog-to-digital converter, liquid crystal display driver module, and other mcu sub-systems. 7.5.6 cgm reference clock (cgmrclk) this is buffered signal of cgmxclk, it is used by the cgm as the phase-locked-loop (pll) reference clock. 7.6 low power modes the wait and stop instructions put the mcu in low-power consumption standby modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) oscillator during break mode mc68HC908LJ12 ? rev. 2.0 technical data motorola oscillator (osc) 99 7.6.1 wait mode the wait instruction has no effect on the oscillator module. cgmxclk, cgmrclk, and iclk continues to drive the mcu modules. 7.6.2 stop mode the stop instruction clears the simoscen signal, and hence the cgmxclk (and cgmrclk) clock stops running. for continuous cgmxclk operation in stop mode, set the stop_xclken to logic 1 before entering stop mode. continuous cgmxclk operation in stop mode allows the rtc module to generate interrupts to wake up the cpu. by default, the internal rc oscillator clock, iclk, continues to run in stop mode. to disable the iclk in stop mode, set the stop_ircdis bit to logic 1 before entering stop mode. 7.7 oscillator during break mode the oscillator circuits continue to drive cgmxclk, cgmrclk, and iclk when the device enters the break state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) technical data mc68HC908LJ12 ? rev. 2.0 100 oscillator (osc) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 101 technical data ? mc68HC908LJ12 section 8. clock generator module (cgm) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.1 oscillator module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.4.2 phase-locked loop circuit (pll) . . . . . . . . . . . . . . . . . . .106 8.4.3 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.4.4 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . .108 8.4.5 manual and automatic pll bandwidth modes. . . . . . . . . .108 8.4.6 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 8.4.7 special programming exceptions . . . . . . . . . . . . . . . . . . .114 8.4.8 base clock selector circuit . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.9 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . 115 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.5.1 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . 116 8.5.2 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . .116 8.5.3 pll analog ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . 116 8.5.4 oscillator output frequency signal (cgmxclk) . . . . . . . 116 8.5.5 cgm reference clock (cgmrclk) . . . . . . . . . . . . . . . . . 116 8.5.6 cgm vco clock output (cgmvclk) . . . . . . . . . . . . . . . . 117 8.5.7 cgm base clock output (cgmout). . . . . . . . . . . . . . . . . 117 8.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 117 8.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 8.6.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 8.6.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . . 120 8.6.3 pll multiplier select registers . . . . . . . . . . . . . . . . . . . . . 122 8.6.4 pll vco range select register . . . . . . . . . . . . . . . . . . . . 123 8.6.5 pll reference divider select register . . . . . . . . . . . . . . . 124 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 102 clock generator module (cgm) motorola 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.8 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 8.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 8.8.3 cgm during break interrupts. . . . . . . . . . . . . . . . . . . . . . . 126 8.9 acquisition/lock time specifications . . . . . . . . . . . . . . . . . . .127 8.9.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . . 127 8.9.2 parametric influences on reaction time . . . . . . . . . . . . . . 127 8.9.3 choosing a filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.2 introduction this section describes the clock generator module (cgm). the cgm generates the base clock signal, cgmout, which is based on either the oscillator clock divided by two or the divided phase-locked loop (pll) clock, cgmpclk, divided by two. cgmout is the clock from which the sim derives the system clocks, including the bus clock, which is at a frequency of cgmout 2. the pll is a frequency generator designed for use with a low frequency crystal (typically 32.768khz) to generate a base frequency and dividing to a maximum bus frequency of 8mhz. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) features mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 103 8.3 features features of the cgm include: phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference low-frequency crystal operation with low-power operation and high-output frequency resolution programmable prescaler for power-of-two increases in frequency programmable hardware voltage-controlled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitter operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition configuration register bit to allow oscillator operation during stop mode 8.4 functional description the cgm consists of three major sub-modules: oscillator module ? the oscillator module generates the constant reference frequency clock, cgmrclk (buffered cgmxclk). phase-locked loop (pll) ? the pll generates the programmable vco frequency clock, cgmvclk, and the divided, cgmpclk. the cgmpclk is one of the reference clocks to the base clock selector circuit. base clock selector circuit ? this software-controlled circuit selects the one of three clocks as the base clock, cgmout: cgmxclk, cgmxclk divided by two, or cgmpclk divided by two. figure 8-1 shows the structure of the cgm. figure 8-2 is a summary of the cgm registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 104 clock generator module (cgm) motorola figure 8-1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator automatic mode control lock detector cgmxclk cgmout cgmvdv interrupt control cgmint cgmrdv pll analog cgmrclk v dda cgmxfc v ssa lock auto acq vpr[1:0] pllie pllf mul[11:0] reference divider vrs[7:0] frequency divider pre[1:0] t0 rtc, adc, lcd phase-locked loop (pll) a b 1 s config2 to sim to sim rds[3:0] r cgmpclk simoscen oscillator (osc) module osc2 osc1 from sim iclk cgmrclk internal rc osc crystal oscillator see section 7. oscillator (osc) . n to sim (and cop) l 2 p 2 e simdiv2 from sim div2clk a b 1 s 2 a b 1 s user mode: cgmout = b reset: a reset: a cgmpclk clock select circuit cgmvclk base f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 105 addr.register name bit 7654321bit 0 $0036 pll control register (ptcl) read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00100000 $0037 pll bandwidth control register (pbwc) read: auto lock acq 0000 r write: reset:00000000 $0038 pll multiplier select register high (pmsh) read: 0000 mul11 mul10 mul9 mul8 write: reset:00000000 $0039 pll multiplier select register low (pmsl) read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 $003a pll vco range select register (pmrs) read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 $003b pll reference divider select register (pmds) read: 0000 rds3 rds2 rds1 rds0 write: reset: 0 00 0 0001 = unimplemented r = reserved notes: 1. when auto = 0, pllie is forced clear and is read-only. 2. when auto = 0, pllf and lock read as clear. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs7:vrs0 = $0, bcs is forced clear and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. figure 8-2. cgm i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 106 clock generator module (cgm) motorola 8.4.1 oscillator module the oscillator module provides two clock outputs cgmxclk and cgmrclk to the cgm module. cgmxclk or cgmxclk divide-by-two can be selected to drive the sim module to generate the system bus clocks. cgmrclk is the reference clock for the phase-lock-loop, to generate a higher frequency clock. the oscillator module also provides the reference clock for the real time clock (rtc) module. see section 7. oscillator (osc) for detailed description on oscillator module. see section 12. real time clock (rtc) for detailed description on rtc. 8.4.2 phase-locked loop circuit (pll) the pll is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. the pll can change between acquisition and tracking modes either automatically or manually. 8.4.3 pll circuits the pll consists of these circuits: voltage-controlled oscillator (vco) reference divider frequency pre-scaler modulo vco frequency divider phase detector loop filter lock detector f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 107 the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and cgmxfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cgmxfc pin changes the frequency within this range. by design, f vrs is equal to the nominal center-of-range frequency, f nom , (38.4 khz) times a linear factor, l, and a power-of-two factor, e, or (l 2 e )f nom . cgmrclk is the pll reference clock, a buffered version of cgmxclk. cgmrclk runs at a frequency, f rclk , and is fed to the pll through a programmable modulo reference divider, which divides f rclk by a factor, r. the divider ? s output is the final reference clock, cgmrdv, running at a frequency, f rdv =f rclk /r. with an external crystal (30khz ? 100khz), always set r = 1 for specified performance. with an external high-frequency clock source, use r to divide the external frequency to between 30khz and 100khz. the vco ? s output clock, cgmvclk, running at a frequency, f vclk , is fed back through a programmable pre-scaler divider and a programmable modulo divider. the pre-scaler divides the vco clock by a power-of-two factor p (the cgmpclk) and the modulo divider reduces the vco clock by a factor, n. the dividers ? output is the vco feedback clock, cgmvdv, running at a frequency, f vdv =f vclk /(n 2 p ). (see 8.4.6 programming the pll for more information.) the phase detector then compares the vco feedback clock, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase difference between the two signals. the loop filter then slightly alters the dc voltage on the external capacitor connected to cgmxfc based on the width and direction of the correction pulse. the filter can make fast or slow corrections depending on its mode, described in 8.4.4 acquisition and tracking modes . the value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the frequencies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to the final reference frequency, f rdv . the circuit determines the mode of the pll and the lock condition based on this comparison. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 108 clock generator module (cgm) motorola 8.4.4 acquisition and tracking modes the pll filter is manually or automatically configurable into one of two operating modes: acquisition mode ? in acquisition mode, the filter can make large frequency corrections to the vco. this mode is used at pll start up or when the pll has suffered a severe noise hit and the vco frequency is far off the desired frequency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. (see 8.6.2 pll bandwidth control register .) tracking mode ? in tracking mode, the filter makes only small corrections to the frequency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct, such as when the pll is selected as the base clock source. (see 8.4.8 base clock selector circuit .) the pll is automatically in tracking mode when not in acquisition mode or when the acq bit is set. 8.4.5 manual and automatic pll bandwidth modes the pll can change the bandwidth or operational mode of the loop filter manually or automatically. automatic mode is recommended for most users. in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth control mode also is used to determine when the vco clock, cgmvclk, is safe to use as the source for the base clock, cgmout. (see 8.6.2 pll bandwidth control register .) if pll interrupts are enabled, the software can wait for a pll interrupt request and then check the lock bit. if interrupts are disabled, software can poll the lock bit continuously (during pll start-up, usually) or at periodic intervals. in either case, when the lock bit is set, the vco clock is safe to use as the source for the base clock. (see 8.4.8 base clock selector circuit .) if the vco is selected as the source for the base clock and the lock bit is clear, the pll has suffered a severe noise hit and the software must take appropriate action, depending on the application. (see 8.7 interrupts for information and precautions on using interrupts.) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 109 the following conditions apply when the pll is in automatic bandwidth control mode: the acq bit (see 8.6.2 pll bandwidth control register .) is a read-only indicator of the mode of the filter. (see 8.4.4 acquisition and tracking modes .) the acq bit is set when the vco frequency is within a certain tolerance and is cleared when the vco frequency is out of a certain tolerance. (see 8.9 acquisition/lock time specifications for more information.) the lock bit is a read-only indicator of the locked state of the pll. the lock bit is set when the vco frequency is within a certain tolerance and is cleared when the vco frequency is out of a certain tolerance. (see 8.9 acquisition/lock time specifications for more information.) cpu interrupts can occur if enabled (pllie = 1) when the pll ? s lock condition changes, toggling the lock bit. (see 8.6.1 pll control register .) the pll also may operate in manual mode (auto = 0). manual mode is used by systems that do not require an indicator of the lock condition for proper operation. such systems typically operate well below f busmax . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 110 clock generator module (cgm) motorola the following conditions apply when in manual mode: acq is a writable control bit that controls the mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. before entering tracking mode (acq = 1), software must wait a given time, t acq (see 8.9 acquisition/lock time specifications .), after turning on the pll by setting pllon in the pll control register (pctl). software must wait a given time, t al , after entering tracking mode before selecting the pll as the clock source to cgmout (bcs = 1). the lock bit is disabled. cpu interrupts from the cgm are disabled. 8.4.6 programming the pll the following procedure shows how to program the pll. note: the round function in the following equations means that the real number should be rounded to the nearest integer number. 1. choose the desired bus frequency, f busdes . 2. calculate the desired vco frequency, f vclkdes . where p is the power of two multiplier, and can be 0, 1, 2, or 3 3. choose a practical pll reference frequency, f rclk , and the reference clock divider, r. typically, the reference is 32.768khz and r = 1. frequency errors to the pll are corrected at a rate of f rclk /r. for stability and lock time reduction, this rate must be as fast as possible. the vco frequency must be an integer multiple of this rate. f vclkdes 2 p f cgmpclk 2 p 4 f busdes == f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 111 the relationship between the vco frequency, f vclk , and the reference frequency, f rclk , is where n is the integer range multiplier, between 1 and 4095. in cases where desired bus frequency has some tolerance, choose f rclk to a value determined either by other module requirements (such as modules which are clocked by cgmxclk), cost requirements, or ideally, as high as the specified range allows. see section 23. electrical specifications . choose the reference divider, r = 1. when the tolerance on the bus frequency is tight, choose f rclk to an integer divisor of f busdes , and r = 1. if f rclk cannot meet this requirement, use the following equation to solve for r with practical choices of f rclk , and choose the f rclk that gives the lowest r. 4. calculate n: 5. calculate and verify the adequacy of the vco and bus frequencies f vclk and f bus . f vclk 2 p n r ----------- f rclk () = r round r max f vclkdes f rclk -------------------------- ?? ?? ?? integer f vclkdes f rclk -------------------------- ?? ?? ?? ? ?? ?? ?? = n round rf vclkdes f rclk 2 p ------------------------------------ - ?? ?? ?? = f bus f vclk 2 p 4 ----------- = f vclk 2 p n r ----------- f rclk () = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 112 clock generator module (cgm) motorola 6. select the vco ? s power-of-two range multiplier e, according to this table: 7. select a vco linear range multiplier, l, where f nom = 38.4khz 8. calculate and verify the adequacy of the vco programmed center-of-range frequency, f vrs . the center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the pll. for proper operation, 9. verify the choice of p, r, n, e, and l by comparing f vclk to f vrs and f vclkdes . for proper operation, f vclk must be within the application ? s tolerance of f vclkdes , and f vrs must be as close as possible to f vclk. note: exceeding the recommended maximum bus frequency or vco frequency can crash the mcu. frequency range e 0 < f vclk < 9,830,400 0 9,830,400 f vclk < 19,660,800 1 19,660,800 f vclk < 39,321,600 2 note: do not program e to a value of 3. l round f vclk 2 e f nom -------------------------- ?? ?? ?? = f vrs l2 e () f nom = f vrs f vclk ? f nom 2 e 2 -------------------------- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 113 10. program the pll registers accordingly: a. in the pre bits of the pll control register (pctl), program the binary equivalent of p. b. in the vpr bits of the pll control register (pctl), program the binary equivalent of e. c. in the pll multiplier select register low (pmsl) and the pll multiplier select register high (pmsh), program the binary equivalent of n. d. in the pll vco range select register (pmrs), program the binary coded equivalent of l. e. in the pll reference divider select register (pmds), program the binary coded equivalent of r. note: the values for p, e, n, l, and r can only be programmed when the pll is off (pllon = 0). table 8-1 provides numeric examples (numbers are in hexadecimal notation): table 8-1. numeric examples cgmvclk cgmpclk f bus f rclk rnpel 8.0 mhz 8.0 mhz 2.0 mhz 32.768 khz 1 f5 0 0 d1 9.8304 mhz 9.8304 mhz 2.4576 mhz 32.768 khz 1 12c 0 1 80 10.0 mhz 10.0 mhz 2.5 mhz 32.768 khz 1 132 0 1 83 16 mhz 16 mhz 4.0 mhz 32.768 khz 1 1e9 0 1 d1 19.6608 mhz 19.6608 mhz 4.9152 mhz 32.768 khz 1 258 0 2 80 20 mhz 20 mhz 5.0 mhz 32.768 khz 1 263 0 2 82 29.4912 mhz 29.4912 mhz 7.3728 mhz 32.768 khz 1 384 0 2 c0 32 mhz 32 mhz 8.0 mhz 32.768 khz 1 3d1 0 2 d0 32 mhz 16 mhz 4.0 mhz 32.768 khz 1 1e9 1 2 d0 32 mhz 8 mhz 2.0 mhz 32.768 khz 1 f5 2 2 d0 32 mhz 4 mhz 1.0 mhz 32.768 khz 1 7b 3 2 d0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 114 clock generator module (cgm) motorola 8.4.7 special programming exceptions the programming method described in 8.4.6 programming the pll does not account for three possible exceptions. a value of 0 for r, n, or l is meaningless when used in the equations given. to account for these exceptions: a 0 value for r or n is interpreted exactly the same as a value of 1. a 0 value for l disables the pll and prevents its selection as the source for the base clock. (see 8.4.8 base clock selector circuit .) 8.4.8 base clock selector circuit this circuit is used to select either the oscillator clock, cgmxclk, or the divided vco clock, cgmpclk, as the source of the base clock, cgmout. the two input clocks go through a transition control circuit that waits up to three cgmxclk cycles and three cgmpclk cycles to change from one clock source to the other. during this time, cgmout is held in stasis. the output of the transition control circuit is then divided by two to correct the duty cycle. therefore, the bus clock frequency, which is one-half of cgmout, is one-fourth the frequency of the selected clock (cgmxclk or cgmpclk). for the cgmxclk, the divide-by-2 can be by-passed by setting the div2clk bit in the config2 register. therefore, the bus clock frequency can be one-half of cgmxclk. the bcs bit in the pll control register (pctl) selects which clock drives cgmout. the divided vco clock cannot be selected as the base clock source if the pll is not turned on. the pll cannot be turned off if the divided vco clock is selected. the pll cannot be turned on or off simultaneously with the selection or deselection of the divided vco clock. the divided vco clock also cannot be selected as the base clock source if the factor l is programmed to a 0. this value would set up a condition inconsistent with the operation of the pll, so that the pll would be disabled and the oscillator clock would be forced as the source of the base clock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) i/o signals mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 115 8.4.9 cgm external connections in its typical configuration, the cgm requires up to four external components. figure 8-3 shows the external components for the pll: bypass capacitor, c byp filter network care should be taken with pcb routing in order to minimize signal cross talk and noise. (see 8.9 acquisition/lock time specifications for routing information, filter network and its effects on pll performance.) figure 8-3. cgm external connections 8.5 i/o signals the following paragraphs describe the cgm i/o signals. c byp note: filter network in box can be replaced with a 0.47 f capacitor, but will degrade stability. 10 k ? 0.01 f 0.033 f 0.1 f v ssa v dda cgmxfc v dd mcu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 116 clock generator module (cgm) motorola 8.5.1 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to filter out phase corrections. an external filter network is connected to this pin. (see figure 8-3 .) note: to prevent noise problems, the filter network should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other signals across the network. 8.5.2 pll analog power pin (v dda ) v dda is a power pin used by the analog portions of the pll. connect the v dda pin to the same voltage potential as the v dd pin. note: route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 8.5.3 pll analog ground pin (v ssa ) v ssa is a ground pin used by the analog portions of the pll. connect the v ssa pin to the same voltage potential as the v ss pin. note: route v ssa carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. note: on this mcu, the v ssa is physically bonded to the v ss pin. 8.5.4 oscillator output frequency signal (cgmxclk) cgmxclk is the oscillator output signal. it runs at the full speed of the oscillator, and is generated directly from the crystal oscillator circuit, the rc oscillator circuit, or the internal oscillator circuit. 8.5.5 cgm reference clock (cgmrclk) cgmrclk is a buffered version of cgmxclk, this clock is the reference clock for the phase-locked-loop circuit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 117 8.5.6 cgm vco clock output (cgmvclk) cgmvclk is the clock output from the vco. 8.5.7 cgm base clock output (cgmout) cgmout is the clock output of the cgm. this signal goes to the sim, which generates the mcu clocks. cgmout is a 50 percent duty cycle clock running at twice the bus frequency. cgmout is software programmable to be equal to cgmxclk, cgmxclk divided by two, or cgmpclk divided by two. 8.5.8 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. 8.6 cgm registers the following registers control and monitor operation of the cgm: pll control register (pctl) (see 8.6.1 pll control register .) pll bandwidth control register (pbwc) (see 8.6.2 pll bandwidth control register .) pll multiplier select registers (pmsh and pmsl) (see 8.6.3 pll multiplier select registers .) pll vco range select register (pmrs) (see 8.6.4 pll vco range select register .) pll reference divider select register (pmds) (see 8.6.5 pll reference divider select register .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 118 clock generator module (cgm) motorola 8.6.1 pll control register the pll control register (pctl) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the vco power-of-two range selector bits. pllie ? pll interrupt enable bit this read/write bit enables the pll to generate an interrupt request when the lock bit toggles, setting the pll flag, pllf. when the auto bit in the pll bandwidth control register (pbwc) is clear, pllie cannot be written and reads as logic 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll interrupt flag bit this read-only bit is set whenever the lock bit toggles. pllf generates an interrupt request if the pllie bit also is set. pllf always reads as logic 0 when the auto bit in the pll bandwidth control register (pbwc) is clear. clear the pllf bit by reading the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: do not inadvertently clear the pllf bit. any read or read-modify-write operation on the pll control register clears the pllf bit. address: $0036 bit 7654321bit 0 read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00100000 = unimplemented figure 8-4. pll control register (pctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 119 pllon ? pll on bit this read/write bit activates the pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, cgmout (bcs = 1). (see 8.4.8 base clock selector circuit .) reset sets this bit so that the loop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit selects either the oscillator output, cgmxclk, or the divided vco clock, cgmpclk, as the source of the cgm output, cgmout. cgmout frequency is one-half the frequency of the selected clock. bcs cannot be set while the pllon bit is clear. after toggling bcs, it may take up to three cgmxclk and three cgmpclk cycles to complete the transition from one source clock to the other. during the transition, cgmout is held in stasis. (see 8.4.8 base clock selector circuit .) reset clears the bcs bit. 1 = cgmpclk divided by two drives cgmout 0 = cgmxclk divided by two drives cgmout note: pllon and bcs have built-in protection that prevents the base clock selector circuit from selecting the vco clock as the source of the base clock if the pll is off. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmpclk requires two writes to the pll control register. (see 8.4.8 base clock selector circuit .) pre1 and pre0 ? prescaler program bits these read/write bits control a prescaler that selects the prescaler power-of-two multiplier, p. (see 8.4.3 pll circuits and 8.4.6 programming the pll .) pre1 and pre0 cannot be written when the pllon bit is set. reset clears these bits. these prescaler bits affects the relationship between the vco clock and the final system bus clock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 120 clock generator module (cgm) motorola vpr1 and vpr0 ? vco power-of-two range select bits these read/write bits control the vco ? s hardware power-of-two range multiplier e that, in conjunction with l (see 8.4.3 pll circuits , 8.4.6 programming the pll , and 8.6.4 pll vco range select register .) controls the hardware center-of-range frequency, f vrs . vpr1:vpr0 cannot be written when the pllon bit is set. reset clears these bits. 8.6.2 pll bandwidth control register the pll bandwidth control register (pbwc): selects automatic or manual (software-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode, indicates when the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode table 8-2. pre 1 and pre0 programming pre1 and pre0 p prescaler multiplier 00 0 1 01 1 2 10 2 4 11 3 8 table 8-3. vpr1 and vpr0 programming vpr1 and vpr0 e vco power-of-two range multiplier 00 0 1 01 1 2 10 2 4 note: do not program e to a value of 3. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 121 auto ? automatic bandwidth control bit this read/write bit selects automatic or manual bandwidth control. when initializing the pll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is locked (running at the programmed frequency). when the auto bit is clear, lock reads as logic 0 and has no meaning. the write one function of this bit is reserved for test, so this bit must always be written a 0. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency incorrect or unlocked acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tracking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisition or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. reset clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode address: $0037 bit 7654321bit 0 read: auto lock acq 0000 r write: reset:00000000 = unimplemented r= reserved figure 8-5. pll bandwidth control register (pbwcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 122 clock generator module (cgm) motorola 8.6.3 pll multiplier select registers the pll multiplier select registers (pmsh and pmsl) contain the programming information for the modulo feedback divider. mul[11:0] ? multiplier select bits these read/write bits control the modulo feedback divider that selects the vco frequency multiplier n. (see 8.4.3 pll circuits and 8.4.6 programming the pll .) a value of $0000 in the multiplier select registers configure the modulo feedback divider the same as a value of $0001. reset initializes the registers to $0040 for a default multiply value of 64. note: the multiplier select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1). address: $0038 bit 7654321bit 0 read: 0 0 0 0 mul11 mul10 mul9 mul8 write: reset:00000000 = unimplemented figure 8-6. pll multiplier select register high (pmsh) address: $0039 bit 7654321bit 0 read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 figure 8-7. pll multiplier select register low (pmsl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 123 8.6.4 pll vco range select register the pll vco range select register (pmrs) contains the programming information required for the hardware configuration of the vco. vrs[7:0] ? vco range select bits these read/write bits control the hardware center-of-range linear multiplier l which, in conjunction with e (see 8.4.3 pll circuits , 8.4.6 programming the pll , and 8.6.1 pll control register .), controls the hardware center-of-range frequency, f vrs . vrs[7:0] cannot be written when the pllon bit in the pctl is set. (see 8.4.7 special programming exceptions .) a value of $00 in the vco range select register disables the pll and clears the bcs bit in the pll control register (pctl). (see 8.4.8 base clock selector circuit and 8.4.7 special programming exceptions .). reset initializes the register to $40 for a default range multiply value of 64. note: the vco range select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1) and such that the vco clock cannot be selected as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the pll vco range select register must be programmed correctly. incorrect programming can result in failure of the pll to achieve lock. address: $003a bit 7654321bit 0 read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 figure 8-8. pll vco range select register (pmrs) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 124 clock generator module (cgm) motorola 8.6.5 pll reference divider select register the pll reference divider select register (pmds) contains the programming information for the modulo reference divider. rds[3:0] ? reference divider select bits these read/write bits control the modulo reference divider that selects the reference division factor, r. (see 8.4.3 pll circuits and 8.4.6 programming the pll .) rds[3:0] cannot be written when the pllon bit in the pctl is set. a value of $00 in the reference divider select register configures the reference divider the same as a value of $01. (see 8.4.7 special programming exceptions .) reset initializes the register to $01 for a default divide value of 1. note: the reference divider select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1). note: the default divide value of 1 is recommended for all applications. address: $003b bit 7654321bit 0 read: 0 0 0 0 rds3 rds2 rds1 rds0 write: reset: 0 00 0 0001 = unimplemented figure 8-9. pll reference divider select register (pmds) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) interrupts mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 125 8.7 interrupts when the auto bit is set in the pll bandwidth control register (pbwc), the pll can generate a cpu interrupt request every time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts are enabled or not. when the auto bit is clear, cpu interrupts from the pll are disabled and pllf reads as logic 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit from lock. when the pll enters lock, the divided vco clock, cgmpclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precautions should be taken. if the application is not frequency sensitive, interrupts should be disabled to prevent pll interrupt service routines from impeding software performance or from exceeding stack limitations. note: software can select the cgmpclk divided by two as the cgmout source even if the pll is not locked (lock = 0). therefore, software should make sure the pll is locked before setting the bcs bit. 8.8 special modes the wait instruction puts the mcu in low power-consumption standby modes. 8.8.1 wait mode the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl) to save power. less power-sensitive applications can disengage the pll without turning it off, so that the pll clock is immediately available at wait exit. this would be the case also when the pll is to wake the mcu from wait mode, such as when the pll is first enabled and waiting for lock or lock is lost. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 126 clock generator module (cgm) motorola 8.8.2 stop mode if the oscillator stop mode enable bit (stop_xclken in config2 register) is configured to disabled the oscillator in stop mode, then the stop instruction disables the cgm (oscillator and phase locked loop) and holds low all cgm outputs (cgmout, cgmvclk, cgmpclk, and cgmint). if the stop instruction is executed with the divided vco clock, cgmpclk, divided by two driving cgmout, the pll automatically clears the bcs bit in the pll control register (pctl), thereby selecting the oscillator clock, cgmxclk, divided by two as the source of cgmout. when the mcu recovers from stop, the crystal clock divided by two drives cgmout and bcs remains clear. if the oscillator stop mode enable bit is configured for continuous oscillator operation in stop mode, then the phase locked loop is shut off but the cgmxclk will continue to drive the sim and other mcu sub- systems. 8.8.3 cgm during break interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 9.8.3 sim break flag control register .) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the pllf bit during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write the pll control register during the break state without affecting the pllf bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) acquisition/lock time specifications mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 127 8.9 acquisition/lock time specifications the acquisition and lock times of the pll are, in many applications, the most critical pll design parameters. proper design and use of the pll ensures the highest stability and lowest acquisition/lock times. 8.9.1 acquisition/lock time definitions typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. therefore, the reaction time is constant in this definition, regardless of the size of the step input. for example, consider a system with a 5 percent acquisition time tolerance. if a command instructs the system to change from 0hz to 1mhz, the acquisition time is the time taken for the frequency to reach 1mhz 50khz. 50khz = 5% of the 1mhz step input. if the system is operating at 1mhz and suffers a ? 100khz noise hit, the acquisition time is the time taken to return from 900khz to 1mhz 5khz. 5khz = 5% of the 100khz step input. other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. therefore, the acquisition or lock time varies according to the original error in the output. minor errors may not even be registered. typical pll applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. 8.9.2 parametric influences on reaction time acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. these reaction times are not constant, however. many factors directly and indirectly affect the acquisition time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 128 clock generator module (cgm) motorola the most critical parameter which affects the reaction times of the pll is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corrections. for stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is under user control via the choice of crystal frequency f xclk and the r value programmed in the reference divider. (see 8.4.3 pll circuits , 8.4.6 programming the pll , and 8.6.5 pll reference divider select register .) another critical parameter is the external filter network. the pll modifies the voltage on the vco by adding or subtracting charge from capacitors in this network. therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitance. the size of the capacitor also is related to the stability of the pll. if the capacitor is too small, the pll cannot make small enough adjustments to the voltage and the system cannot lock. if the capacitor is too large, the pll may not be able to adjust the voltage in a reasonable time. (see 8.9.3 choosing a filter .) also important is the operating voltage potential applied to v dda . the power supply potential alters the characteristics of the pll. a fixed value is best. variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the pll. temperature and processing also can affect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limits. external factors, however, can cause drastic changes in the operation of the pll. these factors include noise injected into the pll through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) acquisition/lock time specifications mc68HC908LJ12 ? rev. 2.0 technical data motorola clock generator module (cgm) 129 8.9.3 choosing a filter as described in 8.9.2 parametric influences on reaction time , the external filter network is critical to the stability and reaction time of the pll. the pll is also dependent on reference frequency and supply voltage. either of the filter networks in figure 8-10 is recommended when using a 32.768khz reference clock (cgmrclk). figure 8-10 (a) is used for applications requiring better stability. figure 8-10 (b) is used in low-cost applications where stability is not critical. figure 8-10. pll filter 10 k ? 0.01 f 0.033 f v ssa 0.47 f v ssa (a) (b) cgmxfc cgmxfc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data mc68HC908LJ12 ? rev. 2.0 130 clock generator module (cgm) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola system integration module (sim) 131 technical data ? mc68HC908LJ12 section 9. system integration module (sim) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 134 9.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.3.2 clock start-up from por or lvi reset. . . . . . . . . . . . . . . . 135 9.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . .136 9.4 reset and system initialization. . . . . . . . . . . . . . . . . . . . . . . . 136 9.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.4.2 active resets from internal sources . . . . . . . . . . . . . . . . . 137 9.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.4.2.2 computer operating properly (cop) reset. . . . . . . . . . 139 9.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 140 9.4.2.6 monitor mode entry module reset (modrst) . . . . . . . 140 9.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.5.1 sim counter during power-on reset . . . . . . . . . . . . . . . . 141 9.5.2 sim counter during stop mode recovery . . . . . . . . . . . . . 141 9.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . .141 9.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9.6.1.3 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . 145 9.6.1.4 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . 145 9.6.1.5 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . 147 9.6.1.6 interrupt status register 3 . . . . . . . . . . . . . . . . . . . . . . . 147 9.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.6.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68HC908LJ12 ? rev. 2.0 132 system integration module (sim) motorola 9.6.4 status flag protection in break mode . . . . . . . . . . . . . . . .148 9.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 9.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 9.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.8.1 sim break status register . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.8.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . 153 9.8.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . 154 9.2 introduction this section describes the system integration module (sim). together with the cpu, the sim controls all mcu activities. a block diagram of the sim is shown in figure 9-1 . table 9-1 is a summary of the sim input/output (i/o) registers. the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: bus clock generation and control for cpu and peripherals: ? stop/wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture expandable to 128 interrupt sources table 9-1 shows the internal signal names used in this section. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) introduction mc68HC908LJ12 ? rev. 2.0 technical data motorola system integration module (sim) 133 figure 9-1. sim block diagram stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to cgm, osc) cgmout (from cgm) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock iclk (from osc) 2 v dd internal pullup device table 9-1. signal name conventions signal name description iclk internal rc oscillator clock cgmxclk buffered version of osc1 from the oscillator module cgmpclk pll output and the divided pll output cgmout pll-based or oscillator-based clock output from cgm module (bus clock = cgmout 2) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68HC908LJ12 ? rev. 2.0 134 system integration module (sim) motorola 9.3 sim bus clock control and generation the bus clock generator provides system clock signals for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, cgmout, as shown in figure 9-3 . this clock can come from either the oscillator module or from the on-chip pll. (see section 8. clock generator module (cgm) .) addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) read: 00000if17if16if15 write:rrrrrrrr reset:00000000 = unimplemented r = reserved figure 9-2. sim i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim bus clock control and generation mc68HC908LJ12 ? rev. 2.0 technical data motorola system integration module (sim) 135 figure 9-3. cgm clock signals 9.3.1 bus timing in user mode, the internal bus frequency is either the oscillator output (cgmxclk) divided by four, cgmxclk divided by two, or the pll output (cgmpclk) divided by four. 9.3.2 clock start-up from por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 iclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the ibus clocks start upon completion of the timeout. 2 bus clock generators system integration module monitor mode user mode simoscen oscillator (osc) module osc2 osc1 phase-locked loop (pll) cgmxclk cgmrclk it12 cgmout simdiv2 ptc1 to rtc, adc stop mode clock to rest of mcu it23 to rest of mcu enable signals from config2 iclk sim counter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68HC908LJ12 ? rev. 2.0 136 system integration module (sim) motorola 9.3.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt, break, or reset, the sim allows iclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 iclk cycles. (see 9.7.2 stop mode .) in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 9.4 reset and system initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe:$ffff ($fefe:$feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 9.5 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). (see 9.8 sim registers .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68HC908LJ12 ? rev. 2.0 technical data motorola system integration module (sim) 137 9.4.1 external pin reset the rst pin circuit includes an internal pull-up device. pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 iclk cycles, assuming that neither the por nor the lvi was the source of the reset. see table 9-2 for details. figure 9-4 shows the relative timing. figure 9-4. external reset timing 9.4.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 iclk cycles to allow resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles (see figure 9-5 ). an internal reset can be caused by an illegal address, illegal opcode, cop timeout, lvi, or por (see figure 9-6 ). note: for lvi or por resets, the sim cycles through 4096 + 32 iclk cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 9-5 . table 9-2. pin bit set timing reset type number of cycles required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l cgmout f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68HC908LJ12 ? rev. 2.0 138 system integration module (sim) motorola figure 9-5. internal reset timing the cop reset is asynchronous to the bus clock. figure 9-6. sources of internal reset the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. 9.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 + 32 iclk cycles. thirty-two iclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, these events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables cgmout. internal clocks to the cpu and modules are held inactive for 4096 iclk cycles to allow stabilization of the oscillator. the rst pin is driven low during the oscillator stabilization time. the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high iclk illegal address rst illegal opcode rst coprst lvi por internal reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68HC908LJ12 ? rev. 2.0 technical data motorola system integration module (sim) 139 figure 9-7. por recovery 9.4.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module timeout, write any value to location $ffff. writing to location $ffff clears the cop counter and bits 12 through 5 of the sim counter. the sim counter output, which occurs at least every 2 13 ? 2 4 iclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. the cop module is disabled if the rst pin or the irq pin is held at v tst while the mcu is in monitor mode. the cop module can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v tst on the rst pin disables the cop module. porrst osc1 iclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff irst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68HC908LJ12 ? rev. 2.0 140 system integration module (sim) motorola 9.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the mask option register is logic 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 9.4.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. 9.4.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the lvi trip falling voltage, v tripf . the lvi bit in the sim reset status register (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 + 32 iclk cycles. thirty-two iclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 9.4.2.6 monitor mode entry module reset (modrst) the monitor mode entry module reset (modrst) asserts its output to the sim when monitor mode is entered in the condition where the reset vectors are blank ($ff). (see section 10. monitor rom (mon) .) when modrst gets asserted, an internal reset occurs. the sim actively pulls down the rst pin for all internal reset sources. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim counter mc68HC908LJ12 ? rev. 2.0 technical data motorola system integration module (sim) 141 9.5 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly module (cop). the sim counter overflow supplies the clock for the cop module. the sim counter is 12 bits long and is clocked by the falling edge of iclk. 9.5.1 sim counter during power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the clock generation module (cgm) to drive the bus clock state machine. 9.5.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configuration register 1 (config1). if the ssrec bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 iclk cycles down to 32 iclk cycles. this is ideal for applications using canned oscillators that do not require long start-up times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared. 9.5.3 sim counter and reset states external reset has no effect on the sim counter. (see 9.7.2 stop mode for details.) the sim counter is free-running after all reset states. (see 9.4.2 active resets from internal sources for counter control and internal reset recovery sequences.) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68HC908LJ12 ? rev. 2.0 142 system integration module (sim) motorola 9.6 exception control normal, sequential program execution can be changed in three different ways: interrupts: ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts 9.6.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 9-8 shows interrupt entry timing, and figure 9-9 shows interrupt recovery timing. figure 9-8. interrupt entry timing figure 9-9. interrupt recovery timing module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i-bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[15:8] pc ? 1[7:0] opcode operand i-bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68HC908LJ12 ? rev. 2.0 technical data motorola system integration module (sim) 143 interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared). (see figure 9-10 .) figure 9-10. interrupt processing no no no yes no no yes yes as many interrupts i bit set? from reset break i-bit set? irq interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers stack cpu registers set i-bit load pc with interrupt vector execute instruction yes yes as exist on chip interrupt? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68HC908LJ12 ? rev. 2.0 144 system integration module (sim) motorola 9.6.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 9-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. figure 9-11 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68HC908LJ12 ? rev. 2.0 technical data motorola system integration module (sim) 145 9.6.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 9.6.1.3 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 9-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. 9.6.1.4 interrupt status register 1 if6 ? if1 ? interrupt flags 6 ? 1 these flags indicate the presence of interrupt requests from the sources shown in table 9-3 . 1 = interrupt request present 0 = no interrupt request present bit 0 and bit 1 ? always read 0 address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r=reserved figure 9-12. interrupt status register 1 (int1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68HC908LJ12 ? rev. 2.0 146 system integration module (sim) motorola table 9-3. vector addresses priority int flag address vector lowest highest if17 $ffda real time clock vector (high) $ffdb real time clock vector (low) if16 $ffdc adc conversion complete vector (high) $ffdd adc conversion complete vector (low) if15 $ffde keyboard vector (high) $ffdf keyboard vector (low) if14 $ffe0 sci transmit vector (high) $ffe1 sci transmit vector (low) if13 $ffe2 sci receive vector (high) $ffe3 sci receive vector (low) if12 $ffe4 sci error vector (high) $ffe5 sci error vector (low) if11 $ffe6 spi receive vector (high) $ffe7 spi receive vector (low) if10 $ffe8 spi transmit vector (high) $ffe9 spi transmit vector (low) if9 $ffea tim2 overflow vector (high) $ffeb tim2 overflow vector (low) if8 $ffec tim2 channel 1 vector (high) $ffed tim2 channel 1 vector (low) if7 $ffee tim2 channel 0 vector (high) $ffef tim2 channel 0 vector (low) if6 $fff0 tim1 overflow vector (high) $fff1 tim1 overflow vector (low) if5 $fff2 tim1 channel 1 vector (high) $fff3 tim1 channel 1 vector (low) if4 $fff4 tim1 channel 0 vector (high) $fff5 tim1 channel 0 vector (low) if3 $fff6 pll vector (high) $fff7 pll vector (low) if2 $fff8 lvi vector (high) $fff9 lvi vector (low) if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) $ffff reset vector (low) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68HC908LJ12 ? rev. 2.0 technical data motorola system integration module (sim) 147 9.6.1.5 interrupt status register 2 if14 ? if7 ? interrupt flags 14 ? 7 these flags indicate the presence of interrupt requests from the sources shown in table 9-3 . 1 = interrupt request present 0 = no interrupt request present 9.6.1.6 interrupt status register 3 if17 ? if15 ? interrupt flags 17 ? 15 these flags indicate the presence of an interrupt request from the source shown in table 9-3 . 1 = interrupt request present 0 = no interrupt request present address: $fe05 bit 7654321bit 0 read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 r=reserved figure 9-13. interrupt status register 2 (int2) address: $fe06 bit 7654321bit 0 read: 00000if17if16if15 write:rrrrrrrr reset:00000000 r=reserved figure 9-14. interrupt status register 3 (int3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68HC908LJ12 ? rev. 2.0 148 system integration module (sim) motorola 9.6.2 reset all reset sources always have equal and highest priority and cannot be arbitrated. 9.6.3 break interrupts the break module can stop normal program flow at a software- programmable break point by asserting its break interrupt output. (see section 22. break module (brk) .) the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 9.6.4 status flag protection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (bcfe) in the sim break flag control register (sbfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mode without losing status flag information. setting the bcfe bit enables the clearing mechanisms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a 2-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power modes mc68HC908LJ12 ? rev. 2.0 technical data motorola system integration module (sim) 149 9.7 low-power modes executing the wait or stop instruction puts the mcu in a low power- consumption mode for standby situations. the sim holds the cpu in a non-clocked state. the operation of each of these modes is described in the following subsections. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 9.7.1 wait mode in wait mode, the cpu clocks are inactive while the peripheral clocks continue to run. figure 9-15 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wait instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode also can be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in the mask option register is logic 0, then the computer operating properly module (cop) is enabled and remains active in wait mode. figure 9-15. wait mode entry timing figure 9-16 and figure 9-17 show the timing for wait recovery. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68HC908LJ12 ? rev. 2.0 150 system integration module (sim) motorola figure 9-16. wait recovery from interrupt or break figure 9-17. wait recovery from internal reset 9.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. the sim disables the clock generator module output (cgmout) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the configuration register 1 (config1). if ssrec is set, stop recovery is reduced from the normal delay of 4096 iclk cycles down to 32. this is ideal for applications using canned oscillators that do not require long start-up times from stop mode. note: external crystal applications should use the full stop recovery time by clearing the ssrec bit. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 iclk 32 cycles 32 cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers mc68HC908LJ12 ? rev. 2.0 technical data motorola system integration module (sim) 151 a break interrupt during stop mode sets the sim break stop/wait bit (sbsw) in the sim break status register (sbsr). the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 9-18 shows stop mode entry timing. note: to minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0. figure 9-18. stop mode entry timing figure 9-19. stop mode recovery from interrupt or break 9.8 sim registers the sim has three memory-mapped registers: sim break status register (sbsr) ? $fe00 sim reset status register (srsr) ? $fe01 sim break flag control register (sbfcr) ? $fe03 stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. iclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68HC908LJ12 ? rev. 2.0 152 system integration module (sim) motorola 9.8.1 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from stop mode or wait mode. sbsw ? break wait bit this status bit is set when a break interrupt causes an exit from wait mode or stop mode. clear sbsw by writing a logic 0 to it. reset clears sbsw. 1 = stop mode or wait mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break interrupt routine. the user can modify the return address on the stack by subtracting 1 from it. the following code is an example. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. r= reserved figure 9-20. sim break status register (sbsr) this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ lobyte equ if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers mc68HC908LJ12 ? rev. 2.0 technical data motorola system integration module (sim) 153 9.8.2 sim reset status register this register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared. clear the sim reset status register by reading it. a power-on reset sets the por bit and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset caused by the lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write: reset:10000000 = unimplemented figure 9-21. sim reset status register (srsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68HC908LJ12 ? rev. 2.0 154 system integration module (sim) motorola 9.8.3 sim break flag control register the sim break control register contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 9-22. sim break flag control register (sbfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 155 technical data ? mc68HC908LJ12 section 10. monitor rom (mon) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 10.4.3 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 10.4.4 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10.6 rom-resident routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 10.6.1 prgrnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 10.6.2 erarnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.6.3 ldrnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 10.6.4 mon_prgrnge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 10.6.5 mon_erarnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 10.6.6 mon_ldrnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 10.6.7 ee_write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 10.6.8 ee_read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 156 monitor rom (mon) motorola 10.2 introduction this section describes the monitor rom (mon) and the monitor mode entry methods. the monitor rom allows complete testing of the mcu through a single-wire interface with a host computer. monitor mode entry can be achieved without use of the higher test voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements for in-circuit programming. in addition, to simply user coding, routines are also stored in the monitor rom area for flash memory program /erase and eeprom emulation. 10.3 features features of the monitor rom include: normal user-mode pin functionality one pin dedicated to serial communication between monitor rom and host computer standard mark/space non-return-to-zero (nrz) communication with host computer execution of code in ram or flash flash memory security feature 1 flash memory programming interface enhanced pll (phase-locked loop) option to allow use of external 32.768-khz crystal to generate internal frequency of 2.4576 mhz 960 bytes monitor rom code size ($fc00 ? $fdff and $fe10 ? $ffce) monitor mode entry without high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) standard monitor mode entry if high voltage, v tst , is applied to irq resident routines for in-circuit programming and eeprom emulation 1. no security feature is absolutely secure. however, motorola ? s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 157 10.4 functional description the monitor rom receives and executes commands from a host computer. figure 10-1 shows an example circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute code downloaded into ram by a host computer while most mcu pins retain normal operating mode functions. all communication between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pullup resistor. the monitor code allows enabling the pll to generate the internal clock, provided the reset vector is blank, when the device is being clocked by a low-frequency crystal. this entry method, which is enabled when irq is held low out of reset, is intended to support serial communication/ programming at 9600 baud in monitor mode by stepping up the external frequency (assumed to be 32.768 khz) by a fixed amount to generate the desired internal frequency (2.4576 mhz). since this feature is enabled only when irq is held low out of reset, it cannot be used when the reset vector is non-zero because entry into monitor mode in this case requires v tst on irq . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 158 monitor rom (mon) motorola figure 10-1. monitor mode circuit + + + mc145407 mc74hc125 rst irq cgmxfc osc1 osc2 v ss v dd pta0 v dd 10 k ? 0.1 f 10 k ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f ptc1 v dd b a (see note 1) 5 6 + v dd pta1 pta2 68HC908LJ12 $ffff $fffe reset vectors d c c c d d 6 ? 30 pf 6 ? 30 pf 32.768 khz xtal 10 m ? sw2 sw1 sw4 sw3 (see note 2) (see notes 2 (see note 2) (see note 3) notes: 1. for monitor mode entry when irq = v tst : sw1: position a ? bus clock = cgmxclk 4 or cgmpclk 4 sw1: position b ? bus clock = cgmxclk 2 2. sw2, sw3, and sw4: position c ? enter monitor mode using external oscillator. sw2, sw3, and sw4: position d ? enter monitor mode using external xtal and internal pll. 3. see 23.6 5.0v dc electrical characteristics for irq voltage level requirements. 10 k ? 0.01 f 0.033 f v tst 330 k ? and 3) v refl v refh v dda external oscillator must be used for monitor mode entry when irq = v tst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 159 10.4.1 entering monitor mode table 10-1 shows the pin conditions for entering monitor mode. as specified in the table, monitor mode may be entered after a por and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. if $fffe and $ffff do not contain $ff (programmed state): ? the external clock is 4.9152 mhz with ptc1 low or 9.8304 mhz with ptc1 high ? irq = v tst (pll off) 2. if $fffe and $ffff both contain $ff (erased state): ? the external clock is 9.8304 mhz ? irq = v dd (this can be implemented through the internal irq pullup; pll off) 3. if $fffe and $ffff both contain $ff (erased state): ? the external clock is 32.768 khz (crystal) ? irq = v ss (this setting initiates the pll to boost the external 32.768 khz to an internal bus frequency of 2.4576 mhz) if v tst is applied to irq and ptc1 is low upon monitor mode entry (above condition set 1), the bus frequency is a divide-by-two of the input clock. if ptc1 is high with v tst applied to irq upon monitor mode entry, the bus frequency will be a divide-by-four of the input clock. holding the ptc1 pin low when entering monitor mode causes a bypass of a divide- by-two stage at the oscillator only if v tst is applied to irq . in this event, the cgmout frequency is equal to the cgmxclk frequency, and the osc1 input directly generates internal bus clocks. in this case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. if entering monitor mode without high voltage on irq (above condition set 2 or 3, where applied voltage is either v dd or v ss ), then all port a pin requirements and conditions, including the ptc1 frequency divisor selection, are not in effect. this is to reduce circuit requirements when performing in-circuit programming. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 160 monitor rom (mon) motorola table 10-1. monitor mode signal requirements and options irq rst address $fffe/ $ffff pta2 pta1 pta0 (1) ptc1 external clock (2) bus frequency pll cop baud rate comment xgndx xxxx x 0 xdisabled0no operation until reset goes high v tst (3) v dd or v tst x 01104. 9152 mhz 2.4576 mhz off disabled 9600 pta1 and pta2 voltages only required if irq = v tst ; ptc1 determines frequency divider v tst (3) v dd or v tst x 01119. 8304 mhz 2.4576 mhz off disabled 9600 pta1 and pta2 voltages only required if irq = v tst ; ptc1 determines frequency divider v dd v dd blank "$ffff" x x 1 x 9.8304 mhz 2.4576 mhz off disabled 9600 external frequency always divided by 4 gnd v dd blank "$ffff" x x 1 x 32.768 khz 2.4576 mhz on disabled 9600 pll enabled (bcs set) in monitor code v dd or gnd v tst blank "$ffff" xxxx x ? off enabled ? enters user mode ? will encounter an illegal address reset v dd or gnd v dd or v tst not blankxxxx x ? off enabled ? enters user mode notes : 1. pta0 = 1 if serial communication; pta0 = 0 if parallel communication 2. external clock is derived by a 32.768 khz crystal or a 4.9152/9.8304 mhz off-chip oscillator 3. monitor mode entry by irq = v tst , a 4.9152/9.8304 mhz off-chip oscillator must be used. the mcu internal crystal oscillator circuit is bypassed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 161 note: if the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial por reset. once the part has been programmed, the traditional method of applying a voltage, v tst , to irq must be used to enter monitor mode. the cop module is disabled in monitor mode based on these conditions: if monitor mode was entered as a result of the reset vector being blank (above condition set 2 or 3), the cop is always disabled regardless of the state of irq or rst . if monitor mode was entered with v tst on irq (condition set 1), then the cop is disabled as long as v tst is applied to either irq or rst . the second condition states that as long as v tst is maintained on the irq pin after entering monitor mode, or if v tst is applied to rst after the initial reset to get into monitor mode (when v tst was applied to irq ), then the cop will be disabled. in the latter situation, after v tst is applied to the rst pin, v tst can be removed from the irq pin in the interest of freeing the irq for normal functionality in monitor mode. figure 10-2 shows a simplified diagram of the monitor mode entry when the reset vector is blank and just 1 v dd voltage is applied to the irq pin. an external oscillator of 9.8304 mhz is required for a baud rate of 9600, as the internal bus frequency is automatically set to the external frequency divided by four. enter monitor mode with pin configuration shown in figure 10-1 by pulling rst low and then high. the rising edge of rst latches monitor mode. once monitor mode is latched, the values on the specified pins can change. once out of reset, the mcu waits for the host to send eight security bytes. (see 10.5 security .) after the security bytes, the mcu sends a break signal (10 consecutive logic 0s) to the host, indicating that it is ready to receive a command. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 162 monitor rom (mon) motorola figure 10-2. low-voltage monitor mode entry flowchart in monitor mode, the mcu uses different vectors for reset, swi (software interrupt), and break interrupt than those for user mode. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. note: exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (por). pulling rst low will not exit monitor mode in this situation. table 10-2 summarizes the differences between user mode and monitor mode vectors. is vector blank? por triggered? normal user mode monitor mode execute monitor code no no yes yes por reset table 10-2. mode differences (vectors) modes functions reset vector high reset vector low break vector high break vector low swi vector high swi vector low user $fffe $ffff $fffc $fffd $fffc $fffd monitor $fefe $feff $fefc $fefd $fefc $fefd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 163 10.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. transmit and receive baud rates must be identical. figure 10-3. monitor data format 10.4.3 break signal a start bit (logic 0) followed by nine logic 0 bits is a break signal. when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits and then echoes back the break signal. figure 10-4. break transaction 10.4.4 baud rate the communication baud rate is controlled by the crystal frequency and the state of the ptc1 pin (when irq is set to v tst ) upon entry into monitor mode. when ptc1 is high, the divide by ratio is 1024. if the ptc1 pin is at logic 0 upon entry into monitor mode, the divide by ratio is 512. if monitor mode was entered with v dd on irq , then the divide by ratio is set at 1024, regardless of ptc1. if monitor mode was entered with v ss on irq , then the internal pll steps up the external frequency, presumed to be 32.768 khz, to 2.4576 mhz. these latter two conditions for monitor mode entry require that the reset vector is blank. bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit 2-stop bit delay before zero echo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 164 monitor rom (mon) motorola table 10-3 lists external frequencies required to achieve a standard baud rate of 9600 bps. other standard baud rates can be accomplished using proportionally higher or lower frequency generators. if using a crystal as the clock source, be aware of the upper frequency limit that the internal clock module can handle. see section 23. electrical specifications for this limit. 10.4.5 commands the monitor rom firmware uses these commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) the monitor rom firmware echoes each received byte back to the pta0 pin for error checking. an 11-bit delay at the end of each command allows the host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note: wait one bit time after each echo before sending the next byte. table 10-3. monitor baud rate selection external frequency irq ptc1 internal frequency baud rate (bps) 4.9152 mhz v tst 0 2.4576 mhz 9600 9.8304 mhz v tst 1 2.4576 mhz 9600 9.8304 mhz v dd x 2.4576 mhz 9600 32.768 khz v ss x 2.4576 mhz 9600 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 165 figure 10-5. read transaction figure 10-6. write transaction a brief description of each monitor mode command is given in table 10-4 through table 10-9 . table 10-4. read (read memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes: 2 = data return delay, 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, 2 bit times write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32, 3 1 = echo delay, 2 bit times read read echo sent to monitor address high address high address low data return address low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 166 monitor rom (mon) motorola table 10-5. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-byte order; low byte followed by data byte data returned none opcode $49 command sequence table 10-6. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence write write echo from host address high address high address low address low data data iread iread echo from host data return data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 167 a sequence of iread or iwrite commands can access a block of memory sequentially over the full 64k-byte memory map. table 10-7. iwrite (indexed write) command description write to last address accessed + 1 operand single data byte data returned none opcode $19 command sequence table 10-8. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low-byte order opcode $0c command sequence iwrite iwrite echo from host data data readsp readsp echo from host sp return sp high low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 168 monitor rom (mon) motorola the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instructions. before sending the run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp+5 and sp+6. figure 10-7. stack pointer at monitor mode entry table 10-9. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence run run echo from host condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) security mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 169 10.5 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6 ? $fffd. locations $fff6 ? $fffd contain user- defined data. note: do not leave locations $fff6 ? $fffd blank. for security reasons, program locations $fff6 ? $fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send the eight security bytes on pin pta0. if the received bytes match those at locations $fff6 ? $fffd, the host bypasses the security feature and can read all flash locations and execute code from flash. security remains bypassed until a power-on reset occurs. if the reset was not a power-on reset, security remains bypassed and security code entry is not required. (see figure 10-8 .) figure 10-8. monitor mode entry timing byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pta0 rst v dd 4096 + 32 iclk cycles 256 bus cycles (minimum) 1 4 1 1 2 1 break notes: 2 = data return delay, 2 bit times. 4 = wait 1 bit time before sending next byte. 4 from host from mcu 1 = echo delay, 2 bit times. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 170 monitor rom (mon) motorola upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6 ? $fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. after receiving the eight security bytes from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note: the mcu does not transmit a break character until after the host sends the eight security bits. to determine whether the security code entered is correct, check to see if bit 6 of ram address $40 is set. if it is, then the correct security code has been entered and flash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. after failing the security sequence, the flash module can also be mass erased by executing an erase routine that was downloaded into internal ram. the mass erase operation clears the security code locations so that all eight security bytes become $ff (blank). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) rom-resident routines mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 171 10.6 rom-resident routines eight routines stored in the monitor rom area (thus rom-resident) are provided for flash memory manipulation. six of the eight routines are intended to simply flash program, erase, and load operations. the other two routines are intended to simply the use of the flash memory as eeprom. table 10-10 shows a summary of the rom-resident routines. the routines are designed to be called as stand-alone subroutines in the user program or monitor mode. the parameters that are passed to a routine are in the form of a contiguous data block, stored in ram. the index register (h:x) is loaded with the address of the first byte of the data block (acting as a pointer), and the subroutine is called (jsr). using the start address as a pointer, multiple data blocks can be used, any area of ram be used. a data block has the control and data bytes in a defined order, as shown in figure 10-9 . during the software execution, it does not consume any dedicated ram location, the run-time heap will extend the system stack, all other ram location will not be affected. table 10-10. summary of rom-resident routines routine name routine description call address stack used (bytes) prgrnge program a range of locations $fc06 14 erarnge erase a page or the entire array $fcbe 9 ldrnge loads data from a range of locations $ff30 9 mon_prgrnge program a range of locations in monitor mode $ff28 16 mon_erarnge erase a page or the entire array in monitor mode $ff2c 11 mon_ldrnge loads data from a range of locations in monitor mode $ff24 11 ee_write emulated eeprom write. data size ranges from 2 to 15 bytes at a time. $fc00 17 ee_read emulated eeprom read. data size ranges from 2 to 15 bytes at a time. $fc03 15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 172 monitor rom (mon) motorola figure 10-9. data block format for rom-resident routines the control and data bytes are described below. bus speed ? this one byte indicates the operating bus speed of the mcu. the value of this byte should be equal to 4 times the bus speed. e.g., for a 4mhz bus, the value is 16 ($10). this control byte is useful where the mcu clock source is switched between the pll clock and the crystal clock. data size ? this one byte indicates the number of bytes in the data array that are to be manipulated. the maximum data array size is 255. routines ee_write and ee_read are restricted to manipulate a data array between 2 to 15 bytes. whereas routines erarnge and mon_erarnge do not manipulate a data array, thus, this data size byte has no meaning. start address ? these two bytes, high byte followed by low byte, indicate the start address of the flash memory to be manipulated. data array ? this data array contains data that are to be manipulated. data in this array are programmed to flash memory by the programming routines: prgrnge, mon_prgrnge, ee_write. for the read routines: ldrnge, mon_ldrnge, and ee_read, data is read from flash and stored in this array. data size (datasize) start address high (addrh) start address low (addrl) data 0 data 1 bus speed (bus_spd) file_ptr data n data array $xxxx data block address as pointer ram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) rom-resident routines mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 173 10.6.1 prgrnge prgrnge is used to program a range of flash locations with data loaded into the data array. the start location of the flash to be programmed is specified by the address addrh:addrl and the number of bytes from this location is specified by datasize. the maximum number of bytes that can be programmed in one routine call is 255 bytes (max. datasize is 255). addrh:addrl do not need to be at a page boundary, the routine handles any boundary misalignment during programming. a check to see that all bytes in the specified range are erased is not performed by this routine prior programming. nor does this routine do a verification after programming, so there is no return confirmation that programming was successful. user must assure that the range specified is first erased. the coding example below is to program 64 bytes of data starting at flash location $ef00, with a bus speed of 4.9152 mhz. the coding assumes the data block is already loaded in ram, with the address pointer, file_ptr, pointing to the first byte of the data block. table 10-11. prgrnge routine routine name prgrnge routine description program a range of locations calling address $fc06 stack used 14 bytes data block format bus speed (bus_spd) data size (datasize) start address high (addrh) start address (addrl) data 1 (data1) : data n (datan) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 174 monitor rom (mon) motorola org ram : file_ptr: bus_spd ds.b 1 ; indicates 4x bus frequency datasize ds.b 1 ; data size to be programmed start_addr ds.w 1 ; flash start address dataarray ds.b 64 ; reserved data array prgrnge equ $fc06 flash_start equ $ef00 org flash initialisation: mov #20, bus_spd mov #64, datasize ldhx #flash_start sthx start_addr rts main: bsr initialisation : : ldhx file_ptr jsr prgrnge f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) rom-resident routines mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 175 10.6.2 erarnge erarnge is used to erase a range of locations in flash. there are two sizes of erase ranges: a page or the entire array. the erarnge will erase the page (128 consecutive bytes) in flash specified by the address addrh:addrl. this address can be any address within the page. calling erarnge with addrh:addrl equal to $ffff will erase the entire flash array (mass erase). therefore, care must be taken when calling this routine to prevent an accidental mass erase. the erarnge routine do not use a data array. the datasize byte is a dummy byte that is also not used. the coding example below is to perform a page erase, from $ef00 ? $ef7f. the initialization subroutine is the same as the coding example for prgrnge (see 10.6.1 prgrnge ). erarnge equ $fcbe main: bsr initialisation : : ldhx file_ptr jsr erarnge : table 10-12. erarnge routine routine name erarnge routine description erase a page or the entire array calling address $fcbe stack used 9 bytes data block format bus speed (bus_spd) data size (datasize) starting address (addrh) starting address (addrl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 176 monitor rom (mon) motorola 10.6.3 ldrnge ldrnge is used to load the data array in ram with data from a range of flash locations. the start location of flash from where data is retrieved is specified by the address addrh:addrl and the number of bytes from this location is specified by datasize. the maximum number of bytes that can be retrieved in one routine call is 255 bytes. the data retrieved from flash is loaded into the data array in ram. previous data in the data array will be overwritten. user can use this routine to retrieve data from flash that was previously programmed. the coding example below is to retrieve 64 bytes of data starting from $ef00 in flash. the initialization subroutine is the same as the coding example for prgrnge (see 10.6.1 prgrnge ). ldrnge equ $ff30 main: bsr initialization : : ldhx file_ptr jsr ldrnge : table 10-13. ldrnge routine routine name ldrnge routine description loads data from a range of locations calling address $ff30 stack used 9 bytes data block format bus speed (bus_spd) data size (datasize) starting address (addrh) starting address (addrl) data 1 : data n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) rom-resident routines mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 177 10.6.4 mon_prgrnge in monitor mode, mon_prgrnge is used to program a range of flash locations with data loaded into the data array. the mon_prgrnge routine is designed to be used in monitor mode. it performs the same function as the prgrnge routine (see 10.6.1 prgrnge ), except that mon_prgrnge returns to the main program via an swi instruction. after a mon_prgrnge call, the swi instruction will return the control back to the monitor code. table 10-14. mon_prgrnge routine routine name mon_prgrnge routine description program a range of locations, in monitor mode calling address $fc28 stack used 16 bytes data block format bus speed data size starting address (high byte) starting address (low byte) data 1 : data n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 178 monitor rom (mon) motorola 10.6.5 mon_erarnge in monitor mode, erarnge is used to erase a range of locations in flash. the mon_erarnge routine is designed to be used in monitor mode. it performs the same function as the erarnge routine (see 10.6.2 erarnge ), except that mon_erarnge returns to the main program via an swi instruction. after a mon_erarnge call, the swi instruction will return the control back to the monitor code. table 10-15. mon_erarnge routine routine name mon_erarnge routine description erase a page or the entire array, in monitor mode calling address $ff2c stack used 11 bytes data block format bus speed data size starting address (high byte) starting address (low byte) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) rom-resident routines mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 179 10.6.6 mon_ldrnge in monitor mode, ldrnge is used to load the data array in ram with data from a range of flash locations. the mon_ldrnge routine is designed to be used in monitor mode. it performs the same function as the ldrnge routine (see 10.6.3 ldrnge ), except that mon_ldrnge returns to the main program via an swi instruction. after a mon_ldrnge call, the swi instruction will return the control back to the monitor code. table 10-16. icp_ldrnge routine routine name mon_ldrnge routine description loads data from a range of locations, in monitor mode calling address $ff24 stack used 11 bytes data block format bus speed data size starting address (high byte) starting address (low byte) data 1 : data n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 180 monitor rom (mon) motorola 10.6.7 ee_write ee_write is used to write a set of data from the data array to flash. the start location of the flash to be programmed is specified by the address addrh:addrl and the number of bytes in the data array is specified by datasize. the minimum number of bytes that can be programmed in one routine call is 2 bytes, the maximum is 15 bytes. addrh:addrl must always be the start of boundary address (the page start address: $xx00 or $0080) and datasize must be the same size when accessing the same page. in some applications, the user may want to repeatedly store and read a set of data from an area of non-volatile memory. this is easily possible when using an eeprom array. as the write and erase operations can be executed on a byte basis. for flash memory, the minimum erase size is the page ? 128 bytes per page for mc68HC908LJ12. if the data array size is less than the page size, writing and erasing to the same page cannot fully utilize the page. unused locations in the page will be wasted. the ee_write routine is designed to emulate the properties similar to the eeprom. allowing a more efficient use of the flash page for data storage. table 10-17. ee_write routine routine name ee_write routine description emulated eeprom write. data size ranges from 2 to 15 bytes at a time. calling address $fc00 stack used 17 bytes data block format bus speed (bus_spd) data size (datasize) (1) starting address (addrh) (2) starting address (addrl) (1) data 1 : data n notes : 1. the minimum data size is 2 bytes. the maximum data size is 15 bytes. 2. the start address must be a page boundary start address, e.g. $xx00 or $xx80. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) rom-resident routines mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 181 when the user dedicates a page of flash for data storage, and the size of the data array defined, each call of the ee_wrtie routine will automatically transfer the data in the data array (in ram) to the next blank block of locations in the flash page. once a page is filled up, the ee_write routine automatically erases the page, and starts reuse the page again. in the 128-byte page, an 8-byte control block is used by the routine to monitor the utilization of the page. in effect, only 120 bytes are used for data storage. (see figure 10-10 ). the page control operations are transparent to the user. figure 10-10. ee_write flash memory usage when using this routine to store a 2-byte data array, the flash page can be programmed 60 times before the an erase is required. in effect, the write/erase endurance is increased by 60 times. when a 15-byte data array is used, the write/erase endurance is increased by 8 times. due to the flash page size limitation, the data array is limited from 2 bytes to 15 bytes. the coding example below uses the $ef00 ? $ee7f page for data storage. the data array size is 15 bytes, and the bus speed is 4.9152 mhz. the coding assumes the data block is already loaded in ram, with the address pointer, file_ptr, pointing to the first byte of the data block. page boundary control: 8 bytes data array data array data array $xx00 or $xx80 page boundary one page = 128 bytes flash f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 182 monitor rom (mon) motorola org ram : file_ptr: bus_spd ds.b 1 ; indicates 4x bus frequency datasize ds.b 1 ; data size to be programmed start_addr ds.w 1 ; flash starting address dataarray ds.b 15 ; reserved data array ee_write equ $fc00 flash_start equ $ef00 org flash initialisation: mov #20, bus_spd mov #15, datasize ldhx #flash_start sthx start_addr rts main: bsr initialisation : : lhdx file_ptr jsr ee_write note: the ee_write routine is unable to check for incorrect data blocks, such as the flash page boundary address and data size. it is the responsibility of the user to ensure the starting address indicated in the data block is at the flash page boundary and the data size is 2 to 15. if the flash page is already programmed with a data array with a different size, the ee_write call will be ignored. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) rom-resident routines mc68HC908LJ12 ? rev. 2.0 technical data motorola monitor rom (mon) 183 10.6.8 ee_read ee_read is used to load the data array in ram with a set of data from flash. the ee_read routine reads data stored by the ee_write routine. an ee_read call will retrieve the last data written to a flash page and loaded into the data array in ram. same as ee_write, the data size indicated by datasize is 2 to 15, and the start address addrh:addrl must the flash page boundary address. the coding example below uses the data stored by the ee_write coding example (see 10.6.7 ee_write ). it loads the 15-byte data set stored in the $ef00 ? $ee7f page to the data array in ram. the initialization subroutine is the same as the coding example for ee_write (see 10.6.7 ee_write ). ee_read equ $fc03 main: bsr initialization : : ldhx file_ptr jsr ee_read : table 10-18. ee_read routine routine name ee_read routine description emulated eeprom read. data size ranges from 2 to 15 bytes at a time. calling address $fc03 stack used 15 bytes data block format bus speed (bus_spd) data size (datasize) starting address (addrh) (1) starting address (addrl) (1) data 1 : data n notes : 1. the start address must be a page boundary start address, e.g. $xx00 or $xx80. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68HC908LJ12 ? rev. 2.0 184 monitor rom (mon) motorola note: the ee_read routine is unable to check for incorrect data blocks, such as the flash page boundary address and data size. it is the responsibility of the user to ensure the starting address indicated in the data block is at the flash page boundary and the data size is 2 to 15. if the flash page is programmed with a data array with a different size, the ee_read call will be ignored. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola timer interface module (tim) 185 technical data ? mc68HC908LJ12 section 11. timer interface module (tim) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 192 11.5.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . .193 11.5.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . .193 11.5.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . 194 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . .195 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 11.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 198 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.10.1 tim status and control register . . . . . . . . . . . . . . . . . . . .200 11.10.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 11.10.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . 203 11.10.4 tim channel status and control registers . . . . . . . . . . . .204 11.10.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68HC908LJ12 ? rev. 2.0 186 timer interface module (tim) motorola 11.2 introduction this section describes the timer interface (tim) module. the tim is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 11-1 is a block diagram of the tim. this particular mcu has two timer interface modules which are denoted as tim1 and tim2. 11.3 features features of the tim include: two input capture/output compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse-width-modulation (pwm) signal generation programmable tim clock input with 7-frequency internal bus clock prescaler selection free-running or modulo up-count operation toggle any channel pin on overflow tim counter stop and reset bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) pin name conventions mc68HC908LJ12 ? rev. 2.0 technical data motorola timer interface module (tim) 187 11.4 pin name conventions the text that follows describes both timers, tim1 and tim2. the tim input/output (i/o) pin names are t[1,2]ch0 (timer channel 0) and t[1,2]ch1 (timer channel 1), where ? 1 ? is used to indicate tim1 and ? 2 ? is used to indicate tim2. the two tims share four i/o pins with four i/o port pins. the full names of the tim i/o pins are listed in table 11-1 . the generic pin names appear in the text that follows. note: references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tch0 may refer generically to t1ch0 and t2ch0, and tch1 may refer to t1ch1 and t2ch1. 11.5 functional description figure 11-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodh:tmodl, control the modulo value of the tim counter. software can read the tim counter value at any time without affecting the counting sequence. the two tim channels (per timer) are programmable independently as input capture or output compare channels. table 11-1. pin name conventions tim generic pin names: t[1,2]ch0 t[1,2]ch1 full tim pin names: tim1 ptb2/t1ch0 ptb3/t1ch1 tim2 ptb4/t2ch0 ptb5/t2ch1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68HC908LJ12 ? rev. 2.0 188 timer interface module (tim) motorola figure 11-1. tim block diagram figure 11-2 summarizes the timer registers. note: references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc. prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock ms1a t[1,2]ch0 t[1,2]ch1 interrupt logic port logic interrupt logic interrupt logic port logic f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola timer interface module (tim) 189 addr.register name bit 7654321bit 0 $0020 timer 1 status and control register (t1sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer 1 counter register high (t1cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 timer 1 counter register low (t1cntl) read: bit 7 654321bit 0 write: reset:00000000 $0023 timer 1 counter modulo register high (t1modh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0024 timer 1 counter modulo register low (t1modl) read: bit 7654321bit 0 write: reset:11111111 $0025 timer 1 channel 0 status and control register (t1sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 timer 1 channel 0 register high (t1ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0027 timer 1 channel 0 register low (t1ch0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 timer 1 channel 1 status and control register (t1sc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 11-2. tim i/o register summary (sheet 1 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68HC908LJ12 ? rev. 2.0 190 timer interface module (tim) motorola $0029 timer 1 channel 1 register high (t1ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a timer 1 channel 1 register low (t1ch1l) read: bit 7654321bit 0 write: reset: indeterminate after reset $002b timer 2 status and control register (t2sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $002c timer 2 counter register high (t2cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $002d timer 2 counter register low (t2cntl) read: bit 7 654321bit 0 write: reset:00000000 $002e timer 2 counter modulo register high (t2modh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $002f timer 2 counter modulo register low (t2modl) read: bit 7654321bit 0 write: reset:11111111 $0030 timer 2 channel 0 status and control register (t2sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0031 timer 2 channel 0 register high (t2ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 11-2. tim i/o register summary (sheet 2 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola timer interface module (tim) 191 11.5.1 tim counter prescaler the tim clock source can be one of the seven prescaler outputs. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register select the tim clock source. 11.5.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tim latches the contents of the tim counter into the tim channel registers, tchxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. $0032 timer 2 channel 0 register low (t2ch0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0033 timer 2 channel 1 status and control register (t2sc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0034 timer 2 channel 1 register high (t2ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0035 timer 2 channel 1 register low (t2ch1l) read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 11-2. tim i/o register summary (sheet 3 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68HC908LJ12 ? rev. 2.0 192 timer interface module (tim) motorola 11.5.3 output compare with the output compare function, the tim can generate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. 11.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 11.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola timer interface module (tim) 193 11.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output compare value in the tim channel 0 registers initially controls the output on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 11.5.4 pulse width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between overflows is the period of the pwm signal. as figure 11-3 shows, the output compare value in the tim channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on output compare if the state of the pwm pulse is logic 1. program the tim to set the pin if the state of the pwm pulse is logic 0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68HC908LJ12 ? rev. 2.0 194 timer interface module (tim) motorola the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000. see 11.10.1 tim status and control register . figure 11-3. pwm period and pulse width the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. 11.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 11.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written. tchx period pulse width overflow overflow overflow output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola timer interface module (tim) 195 use the following methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 11.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68HC908LJ12 ? rev. 2.0 196 timer interface module (tim) motorola note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 11.5.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter and prescaler by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb:msxa. (see table 11-3 .) b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 11-3 .) note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) interrupts mc68HC908LJ12 ? rev. 2.0 technical data motorola timer interface module (tim) 197 setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h:tch0l) initially control the buffered pwm output. tim status control register 0 (tscr0) controls and monitors the pwm signal from the linked channels. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. (see 11.10.4 tim channel status and control registers .) 11.6 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? the tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. tim channel flags (ch1f:ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie = 1. chxf and chxie are in the tim channel x status and control register. 11.7 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68HC908LJ12 ? rev. 2.0 198 timer interface module (tim) motorola 11.7.1 wait mode the tim remains active after the execution of a wait instruction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim before executing the wait instruction. 11.7.2 stop mode the tim is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 11.8 tim during break interrupts a break interrupt stops the tim counter. the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 9.8.3 sim break flag control register .) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o signals mc68HC908LJ12 ? rev. 2.0 technical data motorola timer interface module (tim) 199 11.9 i/o signals port b shares four of its pins with the tim. the four tim channel i/o pins are t1ch0, t1ch1, t2ch0, and t2ch1 as described in 11.4 pin name conventions . each channel i/o pin is programmable independently as an input capture pin or an output compare pin. t1ch0 and t2ch0 can be configured as buffered output compare or buffered pwm pins. 11.10 i/o registers note: references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc. these i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and control registers (tsc0, tsc1) tim channel registers (tch0h:tch0l, tch1h:tch1l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68HC908LJ12 ? rev. 2.0 200 timer interface module (tim) motorola 11.10.1 tim status and control register the tim status and control register (tsc): enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a logic 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bit enables tim overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled address: t1sc, $0020 and t2sc, $002b bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 11-4. tim status and control register (tsc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola timer interface module (tim) 201 tstop ? tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim counter is reset and always reads as logic 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the tim counter as table 11-2 shows. reset clears the ps[2:0] bits. table 11-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 111 not available f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68HC908LJ12 ? rev. 2.0 202 timer interface module (tim) motorola 11.10.2 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. address: t1cnth, $0021 and t2cnth, $002c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented figure 11-5. tim counter registers high (tcnth) address: t1cntl, $0022 and t2cntl, $002d bit 7654321bit 0 read: bit 7 654321bit 0 write: reset:00000000 = unimplemented figure 11-6. tim counter registers low (tcntl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola timer interface module (tim) 203 11.10.3 tim counter modulo registers the read/write tim modulo registers contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note: reset the tim counter before writing to the tim counter modulo registers. address: t1modh, $0023 and t2modh, $002e bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 figure 11-7. tim counter modulo register high (tmodh) address: t1modl, $0024 and t2modl, $002f bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 11-8. tim counter modulo register low (tmodl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68HC908LJ12 ? rev. 2.0 204 timer interface module (tim) motorola 11.10.4 tim channel status and control registers each of the tim channel status and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tim overflow selects 0% and 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation address: t1sc0, $0025 and t2sc0, $0030 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 figure 11-9. tim channel 0 status and control register (tsc0) address: t1sc1, $0028 and t2sc1, $0033 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 11-10. tim channel 1 status and control register (tsc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola timer interface module (tim) 205 chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. when tim cpu interrupt requests are enabled (chxie = 1), clear chxf by reading tim channel x status and control register with chxf set and then writing a logic 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim1 channel 0 and tim2 channel 0 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:elsxa 0:0, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 11-3 . 1 = unbuffered output compare/pwm operation 0 = input capture operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68HC908LJ12 ? rev. 2.0 206 timer interface module (tim) motorola when elsxb:elsxa = 0:0, this read/write bit selects the initial output level of the tchx pin. see table 11-3 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to an i/o port, and pin tchx is available as a general-purpose i/o pin. table 11-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. table 11-3. mode, edge, and level selection msxb:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initial output level high x1 00 pin under port control; initial output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola timer interface module (tim) 207 note: before enabling a tim channel register for input capture operation, make sure that the tchx pin is stable for at least two bus clocks. user software should also clear chxf before setting chxie to avoid any false interrupts. tovx ? toggle on overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow 0 = channel x pin does not toggle on tim counter overflow note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at logic 1, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 11-11 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 11-11. chxmax latency 11.10.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68HC908LJ12 ? rev. 2.0 208 timer interface module (tim) motorola in input capture mode (msxb:msxa = 0:0), reading the high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. address: t1ch0h, $0026 and t2ch0h, $0031 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 11-12. tim channel 0 register high (tch0h) address: t1ch0l, $0027 and t2ch0l $0032 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 11-13. tim channel 0 register low (tch0l) address: t1ch1h, $0029 and t2ch1h, $0034 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 11-14. tim channel 1 register high (tch1h) address: t1ch1l, $002a and t2ch1l, $0035 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 11-15. tim channel 1 register low (tch1l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola real time clock (rtc) 209 technical data ? mc68HC908LJ12 section 12. real time clock (rtc) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12.4.1 time functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.4.2 calendar functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.4.3 alarm functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.4.4 timebase interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.4.5 chronograph functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 12.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 12.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.6 rtc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.6.1 rtc control register 1 (rtccr1) . . . . . . . . . . . . . . . . . . 216 12.6.2 rtc control register 2 (rtccr2) . . . . . . . . . . . . . . . . . . 218 12.6.3 rtc status register (rtcsr). . . . . . . . . . . . . . . . . . . . . .219 12.6.4 alarm minute and hour registers (almr and alhr) . . . .222 12.6.5 second register (secr) . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12.6.6 minute register (minr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12.6.7 hour register (hrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12.6.8 day register (dayr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 12.6.9 month register (mthr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.6.10 year register (yrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.6.11 day-of-week register (dowr) . . . . . . . . . . . . . . . . . . . . 226 12.6.12 chronograph data register (chrr) . . . . . . . . . . . . . . . . . 226 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) technical data mc68HC908LJ12 ? rev. 2.0 210 real time clock (rtc) motorola 12.2 introduction this section describes the real time clock (rtc) module. the rtc provides real time clock and calendar functions with automatic leap year adjustments. other functions include alarm interrupt, periodic interrupts, and a chronograph timer. 12.3 features features of the rtc module include: counter registers for: ? second ? minute ? hour ? day ? day-of-week ? month ? year day counter with automatic month and leap year adjustment 1/100 seconds chronograph counter seven periodic interrupts alarm interrupt addr.register name bit 7654321bit 0 $0042 rtc control register 1 (rtccr1) read: almie chrie dayie hrie minie secie tb1ie tb2ie write: reset:00000000 $0043 rtc control register 2 (rtccr2) read: 0 0 chre rtce 0 xtl2 xtl1 xtl0 write: r chrclr reset:00000000 = unimplemented r = reserved figure 12-1. rtc i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) features mc68HC908LJ12 ? rev. 2.0 technical data motorola real time clock (rtc) 211 $0044 rtc status register (rtcsr) read: almf chrf dayf hrf minf secf tb1f tb2f write: reset:00000000 $0045 alarm minute register (almr) read: 00 am5 am4 am3 am2 am1 am0 write: reset:00000000 $0046 alarm hour register (alhr) read: 000 ah4 ah3 ah2 ah1 ah0 write: reset:00000000 $0047 second register (secr) read: 0 0 sec5 sec4 sec3 sec2 sec1 sec0 write: reset:00000000 $0048 minute register (minr) read: 0 0 min5 min4 min3 min2 min1 min0 write: reset:00000000 $0049 hour register (hrr) read: 0 0 0 hr4 hr3 hr2 hr1 hr0 write: reset:00000000 $004a day register (dayr) read: 0 0 0 day4 day3 day2 day1 day0 write: reset:00000001 $004b month register (mthr) read: 0000 mth3 mth2 mth1 mth0 write: reset:00000001 $004c year register (yrr) read: yr7 yr6 yr5 yr4 yr3 yr2 yr1 yr0 write: reset:00000000 $004d day-of-week register (dowr) read: 00000 dow2 dow1 dow0 write: reset:00000000 $004e chronograph data register (chrr) read: 0 chr6 chr5 chr4 chr3 chr2 chr1 chr0 write: reset:00000000 = unimplemented r = reserved figure 12-1. rtc i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) technical data mc68HC908LJ12 ? rev. 2.0 212 real time clock (rtc) motorola 12.4 functional description the rtc module provides clock indications in seconds, minutes, and hours; calendar indications in day-of-week, day-of-month, month, and year; with automatic adjustment for month and leap year. reading the clock and calendar registers return the current time and date. writing to these registers set the time and date, and the counters will continue to count from the new settings. the alarm interrupt is set for the hour and minute. when the hour and minute counters matches the time set in the alarm hour and minute registers, the alarm flag is set. the alarm can be configured to generate a cpu interrupt request. a 1/100 seconds chronograph counter is provided for timing applications. this counter can be independently enabled or disabled, and cleared at any time. rtc module interrupts include the alarm interrupt and seven periodic interrupts from the clock counters. for proper rtc module operation, one of the following oscillator frequencies (cgmxclk) must be used: 32.768 khz 32.000 khz 38.400 khz 64.000 khz 76.800 khz configuring the xtl[2:0] bits in the rtc control register 2 selects the appropriate prescalers and dividers to divide cgmxclk down to the basic 1hz clock for driving the clock counters. figure 12-2 shows the structure of the rtc module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola real time clock (rtc) 213 figure 12-2. rtc block diagram 000 256 320 640 384 768 100/110 010 101/111 011 1 hz 4 hz 2 hz 100 hz / 128 hz a b sl x xtl[2:0] interrupt 25 32 xtl[2:0] = 000 => x = a xtl[2:0] = 000 => x = b day-of-week counter register alarm hour register comparator minie minf chre hour counter register second counter register day counter register month counter register year counter register chronograph data register logic alarm minute register comparator minute counter register hrie hrf secie secf dayie dayf tb1ie tb1f tb2ie tb2f chrie chrf almie almf cgmxclk 4 5 6 2 2 32 25 2 2 x 1 64 chronograph counter chrclr internal bus rtce 32.768 khz 32.000 khz 38.400 khz 64.000 khz 76.800 khz valid cgmxclk frequencies: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) technical data mc68HC908LJ12 ? rev. 2.0 214 real time clock (rtc) motorola 12.4.1 time functions real time clock functions are provided by the second, minute, and hour counter registers. all three clock counters are able to generate interrupts on every counter increment, providing periodic interrupts for the second (secf), minute (minf), and hour (hrf). a cpu interrupt request is generated if the corresponding enable bit (secie, minie, and hrie) is also set. 12.4.2 calendar functions calendar functions are provided by the day, day-of-week, month, and year counter registers. the roll over of the day counter is automatically adjusted for the month and leap years. the setting for the year counter ranges from 1901 to 2099. the day flag (dayf) is set on every increment of the day counter. a cpu interrupt request is generated if the day interrupt enable bit (dayie) is also set. 12.4.3 alarm functions an alarm function is provided for the minute and hour counters. when minute counter matches the value stored in the alarm minute register, and the hour counter matches the value stored in the alarm hour register, the alarm flag (almf) will be set. a cpu interrupt request is generated if the alarm interrupt enable bit (almie) is also set. 12.4.4 timebase interrupts in addition to the second, minute, hour, and day periodic interrupts generated by the clock functions, the divider circuits generates a 2hz and a 4hz periodic interrupt. these are indicated by the tb1f and tb2f flags. a cpu interrupt request is generated if the corresponding enable bits (tb1ie and tb2ie) is also set. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) low-power modes mc68HC908LJ12 ? rev. 2.0 technical data motorola real time clock (rtc) 215 12.4.5 chronograph functions a 100hz resolution chronograph counter can be enabled by setting the chre bit. the chronograph counter will automatically roll over to zero when the counter reaches 99. if 32.768khz cgmxclk is used, the chronograph counter resolution becomes 128hz. with either 100hz or 128hz resolution, the counter value is converted to 100hz, before it is saved in the chronograph data register. therefore, each chronograph data register increment represents 10ms. 12.5 low-power modes the stop and wait instructions put the mcu in low power- consumption standby modes. 12.5.1 wait mode the rtc module continues normal operation in wait mode. any enabled cpu interrupt request from the rtc can bring the mcu out of wait mode. if the rtc is not required to bring the mcu out of wait mode, power down the rtc by clearing the rtce bit before executing the wait instruction. 12.5.2 stop mode for continuous rtc operation in stop mode, the oscillator stop mode enable bit (stop_xclken in config2 register) must be set before executing the stop instruction. when stop_xclken is set, cgmxclk continues to drive the rtc module, and any enabled cpu interrupt request from the rtc can bring the mcu out of stop mode. if stop_xclken bit is cleared, the rtc module is inactive after the execution of a stop instruction. the stop instruction does not affect rtc register states. rtc module operation resumes after an external interrupt. to further reduce power consumption, the rtc module should be powered-down by clearing the rtce bit before executing the stop instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) technical data mc68HC908LJ12 ? rev. 2.0 216 real time clock (rtc) motorola 12.6 rtc registers the rtc module has thirteen memory-mapped registers: rtc control register 1 (rtccr1) rtc control register 2 (rtccr2) rtc status register (rtcsr) alarm minute and hour registers (almr and alhr) second register (secr) minute register (minr) hour register (hrr) day register (day) month register (mthr) year register (yrr) day of the week register (dowr) chronograph data register (chrr) 12.6.1 rtc control register 1 (rtccr1) the rtc control register 1 (rtccr1) contains the eight interrupt enable bits for rtc interrupt functions. almie ? alarm interrupt enable this read/write bit enables the alarm flag, almf, to generate cpu interrupt requests. reset clears the almie bit. 1 = almf enabled to generate cpu interrupt 0 = almf not enabled to generate cpu interrupt address: $0042 read: almie chrie dayie hrie minie secie tb1ie tb2ie write: reset:00000000 figure 12-3. rtc control register 1 (rtccr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) rtc registers mc68HC908LJ12 ? rev. 2.0 technical data motorola real time clock (rtc) 217 chrie ? chronograph interrupt enable this read/write bit enables the chronograph flag, chrf, to generate cpu interrupt requests. reset clears the chrie bit. 1 = chrf enabled to generate cpu interrupt 0 = chrf not enabled to generate cpu interrupt dayie ? day interrupt enable this read/write bit enables the day flag, dayf, to generate cpu interrupt requests. reset clears the dayie bit. 1 = dayf enabled to generate cpu interrupt 0 = dayf not enabled to generate cpu interrupt hrie ? hour interrupt enable this read/write bit enables the hour flag, hrf, to generate cpu interrupt requests. reset clears the hrie bit. 1 = hrf enabled to generate cpu interrupt 0 = hrf not enabled to generate cpu interrupt minie ? minute interrupt enable this read/write bit enables the minute flag, minf, to generate cpu interrupt requests. reset clears the minie bit. 1 = minf enabled to generate cpu interrupt 0 = minf not enabled to generate cpu interrupt secie ? second interrupt enable this read/write bit enables the second flag, secf, to generate cpu interrupt requests. reset clears the secie bit. 1 = secf enabled to generate cpu interrupt 0 = secf not enabled to generate cpu interrupt tb1ie ? timebase 1 interrupt enable this read/write bit enables the timebase1 flag, tb1f, to generate cpu interrupt requests. reset clears the tb1ie bit. 1 = tb1f enabled to generate cpu interrupt 0 = tb1f not enabled to generate cpu interrupt tb2ie ? timebase 2 interrupt enable this read/write bit enables the timebase2 flag, tb2f, to generate cpu interrupt requests. reset clears the tb2ie bit. 1 = tb2f enabled to generate cpu interrupt 0 = tb2f not enabled to generate cpu interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) technical data mc68HC908LJ12 ? rev. 2.0 218 real time clock (rtc) motorola 12.6.2 rtc control register 2 (rtccr2) the rtc control register 2 (rtccr2) contains control and clock selection bits for rtc operation. chrclr ? chronograph counter clear setting this write-only bit resets the chronograph counter. setting chrclr has no effect on any other registers. counting resumes from $00. chrclr is cleared automatically after the chronograph counter is reset and always reads as logic 0. reset clears the chrclr bit. 1 = chronograph counter cleared 0 = no effect chre ? chronograph enable this read/write bit enables the chronograph counter, the value in the chronograph data register increments by 1 in every 1/100 seconds. when the chronograph counter is disabled (chre = 0), the value in the chronograph data register is held at the count value. reset clears the chre bit. 1 = chronograph counter enabled 0 = chronograph counter disabled rtce ? real time clock enable this read/write bit enables the entire rtc module, allowing all rtc and chronograph operations. disabling the rtc module does not affect the contents in the rtc registers. reset clears the rtce bit. 1 = rtc module enabled 0 = rtc module disabled address: $0043 read: 0 0 chre rtce 0 xtl2 xtl1 xtl0 write: r chrclr reset:00000000 = unimplemented r = reserved figure 12-4. rtc control register 2 (rtccr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) rtc registers mc68HC908LJ12 ? rev. 2.0 technical data motorola real time clock (rtc) 219 xtl[2:0] ? crystal frequency select bits these three bits set the prescalers/dividers for proper operation of the rtc module for various crystal (cgmxclk) input frequencies. the xtl[2:0] bits can only be written once after reset, subsequent writes to these bits will have no effect on its content. table 12-1 shows the xtl[2:0] settings for various cgmxclk frequencies. reset clear the xtl[2:0] bits. 12.6.3 rtc status register (rtcsr) the rtc status register contains eight status flags. when a flag is set and the corresponding interrupt enable bit is also set, a cpu interrupt request is generated. table 12-1. cgmxclk frequency for rtc input reference cgmxclk (1) notes : 1. using crystal frequencies other than these specified will cause incorrect timings in the rtc module. xtl2 xtl1 xtl0 32.768 khz 0 0 0 reserved 001 32.000 khz 0 1 0 38.400 khz 0 1 1 64.000 khz 1 x 0 76.800 khz 1 x 1 address: $0044 read: almf chrf dayf hrf minf secf tb1f tb2f write: reset:00000000 = unimplemented figure 12-5. rtc status register (rtcsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) technical data mc68HC908LJ12 ? rev. 2.0 220 real time clock (rtc) motorola almf ? alarm flag this clearable, read-only bit is set when the value in the rtc hour and minute counters matches the value in the alarm hour and alarm minute registers. when the almie bit in rtccr1 is set, almf generates a cpu interrupt request. in normal operation, clear the almf bit by reading rtcsr with almf set and then reading the alarm hour register (alhr). reset clears almf. 1 = rtc hour and minute counters matches the alarm hour and minute registers 0 = no matching between hour and minute counters and alarm hour and minute registers chrf ? chronograph flag this clearable, read-only bit is set on every tick of the chronograph counter (every counter count). the tick is on every 1/100 or 1/128 seconds (see 12.4.5 chronograph functions ). when the chrie bit in rtccr1 is set, chrf generates a cpu interrupt request. in normal operation, clear the chrf bit by reading rtcsr with chrf set and then reading the chronograph data register (chrr). reset clears chrf. 1 = a chronograph counter tick has occurred 0 = no chronograph counter tick has occurred dayf ? day flag this clearable, read-only bit is set on every increment of the day counter. when the dayie bit in rtccr1 is set, dayf generates a cpu interrupt request. in normal operation, clear the dayf bit by reading rtcsr with dayf set and then reading the day register (dayr). reset clears dayf. 1 = day counter incremented 0 = no day counter incremented hrf ? hour flag this clearable, read-only bit is set on every increment of the hour counter. when the hrie bit in rtccr1 is set, hrf generates a cpu interrupt request. in normal operation, clear the hrf bit by reading rtcsr with hrf set and then reading the hour register (hrr). reset clears hrf. 1 = hour counter incremented 0 = no hour counter incremented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) rtc registers mc68HC908LJ12 ? rev. 2.0 technical data motorola real time clock (rtc) 221 minf ? minute flag this clearable, read-only bit is set on every increment of the minute counter. when the minie bit in rtccr1 is set, minf generates a cpu interrupt request. in normal operation, clear the minf bit by reading rtcsr with minf set and then reading the minute register (minr). reset clears minf. 1 = minute counter incremented 0 = no minute counter incremented secf ? second flag this clearable, read-only bit is set on every increment of the second counter. when the secie bit in rtccr1 is set, secf generates a cpu interrupt request. in normal operation, clear the secf bit by reading rtcsr with secf set and then reading the second register (secr). reset clears secf. 1 = second counter incremented 0 = no second counter incremented tb1f ? timebase 1 flag this clearable, read-only bit is set on every tick of the timebase 1 counter (every 0.5 seconds). when the tb1ie bit in rtccr1 is set, tb1f generates a cpu interrupt request. in normal operation, clear the tb1f bit by reading rtcsr with tb1f set and then reading the chronograph register (chrr). reset clears tb1f. 1 = a timebase 1 tick (0.5s) has occurred 0 = no timebase 1 tick has occurred tb2f ? timebase 2 flag this clearable, read-only bit is set on every tick of the timebase 2 counter (every 0.25 seconds). when the tb2ie bit in rtccr1 is set, tb2f generates a cpu interrupt request. in normal operation, clear the tb2f bit by reading rtcsr with tb2f set and then reading the chronograph register (chrr). reset clears tb2f. 1 = a timebase 2 tick (0.25s) has occurred 0 = no timebase 2 tick has occurred f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) technical data mc68HC908LJ12 ? rev. 2.0 222 real time clock (rtc) motorola 12.6.4 alarm minute and hour registers (almr and alhr) these read/write registers contain the alarm minute and hour values for the hour and minute alarm function. when the hour counter matches the value in the alarm hour register (alhr) and the minute counter matches the value in the alarm minute register (almr), the alarm flag, almf, is set. when almf is set and the alarm interrupt enable bit, almie, is also set, a cpu interrupt request is generated. note: writing values other than 0 to 59, to almr is possible, but the alarm flag will never be set. note: writing values other than 0 to 23, to alhr is possible, but the alarm flag will never be set. address: $0045 read: 00 am5 am4 am3 am2 am1 am0 write: reset:00000000 = unimplemented figure 12-6. alarm minute register (almr) address: $0046 read: 000 ah4 ah3 ah2 ah1 ah0 write: reset:00000000 = unimplemented figure 12-7. alarm hour register (alhr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) rtc registers mc68HC908LJ12 ? rev. 2.0 technical data motorola real time clock (rtc) 223 12.6.5 second register (secr) this read/write register contains the current value of the second counter. this register can be read at any time without affecting the counter count. writing to this register loads the value to the second counter and the counter continues to count from this new value. the second counter rolls over to 0 ($00) after reaching 59 ($4b). writing a value other than 0 to 59 to this register has no effect. 12.6.6 minute register (minr) this read/write register contains the current value of the minute counter. this register can be read at any time without affecting the counter count. writing to this register loads the value to the minute counter and the counter continues to count from this new value. the minute counter rolls over to 0 ($00) after reaching 59 ($4b). writing a value other than 0 to 59 to this register has no effect. address: $0047 read: 0 0 sec5 sec4 sec3 sec2 sec1 sec0 write: reset:00000000 = unimplemented figure 12-8. second register (secr) address: $0048 read: 0 0 min5 min4 min3 min2 min1 min0 write: reset:00000000 = unimplemented figure 12-9. minute register (minr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) technical data mc68HC908LJ12 ? rev. 2.0 224 real time clock (rtc) motorola 12.6.7 hour register (hrr) this read/write register contains the current value of the hour counter. this register can be read at any time without affecting the counter count. writing to this register loads the value to the hour counter and the counter continues to count from this new value. the hour counter rolls over to 0 ($00) after reaching 23 ($17). writing a value other than 0 to 23 to this register has no effect. 12.6.8 day register (dayr) this read/write register contains the current value of the day-of-month counter. this register can be read at any time without affecting the counter count. writing to this register loads the value to the day counter and the counter continues to count from this new value. the day counter rolls over to 1 ($01) after reaching 28 ($1b), 29 ($1c), 30 ($1d), or 31 ($1e), depending on the value in the month and year registers. writing a value that is not valid for the month and year to this register has no effect. address: $0049 read: 0 0 0 hr4 hr3 hr2 hr1 hr0 write: reset:00000000 = unimplemented figure 12-10. hour register (hrr) address: $004a read: 0 0 0 day4 day3 day2 day1 day0 write: reset:00000001 = unimplemented figure 12-11. day register (dayr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) rtc registers mc68HC908LJ12 ? rev. 2.0 technical data motorola real time clock (rtc) 225 12.6.9 month register (mthr) this read/write register contains the current value of the month counter. this register can be read at any time without affecting the counter count. writing to this register loads the value to the month counter and the counter continues to count from this new value. the month counter rolls over to 1 ($01) after reaching 12 ($0b). writing a value other than 1 to 12 to this register has no effect. 12.6.10 year register (yrr) this read/write register contains the current value of the year counter. this register can be read at any time without affecting the counter count. writing to this register loads the value to the year counter and the counter continues to count from this new value. the value stored in this register is a two ? s complement representation of the year, relative to 2000. for example, the year 2008 is represented by 8 ($08), and the year 1979 is presented by ? 11 ($f5). the range of this register is only valid for ? 99 to +99. writing a value other than ? 99 to +99 to this register has no effect. address: $004b read: 0000 mth3 mth2 mth1 mth0 write: reset:00000001 = unimplemented figure 12-12. month register (mthr) address: $004c read: yr7 yr6 yr5 yr4 yr3 yr2 yr1 yr0 write: reset:00000000 figure 12-13. year register (yrr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . real time clock (rtc) technical data mc68HC908LJ12 ? rev. 2.0 226 real time clock (rtc) motorola 12.6.11 day-of-week register (dowr) this read/write register contains the current value of the day-of-week counter. this register can be read at any time without affecting the counter count. writing to this register loads the value to the day-of-week counter and the counter continues to count from this new value. the day-of-week counter value rolls over to 0 ($00) after reaching 6 ($06). writing a value other than 0 to 6 to this register has no effect. 12.6.12 chronograph data register (chrr) this read-only chronograph data register contains the value in the chronograph counter. reset clears the chronograph data register. setting the chronograph counter reset bit (chrclr) also clears the chronograph data register. the chronograph data register has a resolution of 1/100 seconds (10ms). the chronograph counter value rolls over to $00 after reaching $63. address: $004d read: 00000 dow2 dow1 dow0 write: reset:00000000 = unimplemented figure 12-14. day-of-week register (dowr) address: $004e read: 0 chr6 chr5 chr4 chr3 chr2 chr1 chr0 write: reset:00000000 = unimplemented figure 12-15. chronograph data register (chrr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 227 technical data ? mc68HC908LJ12 section 13. infrared serial communications interface module (irsci) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 13.5 irsci module overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 13.6 infrared functional description. . . . . . . . . . . . . . . . . . . . . . . . 232 13.6.1 infrared transmit encoder . . . . . . . . . . . . . . . . . . . . . . . . . 233 13.6.2 infrared receive decoder . . . . . . . . . . . . . . . . . . . . . . . . . 233 13.7 sci functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 13.7.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 13.7.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 13.7.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 13.7.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 237 13.7.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 13.7.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 13.7.2.5 transmitter interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 239 13.7.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 13.7.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 13.7.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . .241 13.7.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 13.7.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 13.7.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .243 13.7.3.6 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 13.7.3.7 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 13.7.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 13.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 13.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 228 infrared serial communications interface module (irsci) motorola 13.9 sci during break module interrupts. . . . . . . . . . . . . . . . . . . . 249 13.10 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.10.1 ptb0/txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . 249 13.10.2 ptb1/rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.11 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.11.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.11.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13.11.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 13.11.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 13.11.5 sci status register 2 (scs2) . . . . . . . . . . . . . . . . . . . . . . 262 13.11.6 sci data register (scdr). . . . . . . . . . . . . . . . . . . . . . . . . 263 13.11.7 sci baud rate register (scbr) . . . . . . . . . . . . . . . . . . . . 264 13.11.8 sci infrared control register . . . . . . . . . . . . . . . . . . . . . . . 267 13.2 introduction this section describes the infrared serial communications interface (irsci) module which allows high-speed asynchronous communications with peripheral devices and other mcus. this irsci consists of an sci module for conventional sci functions and a software programmable infrared encoder/decoder sub-module for encoding/decoding the serial data for connection to infrared leds in remote control applications. note: references to dma (direct-memory access) and associated functions are only valid if the mcu has a dma module. this mcu does not have the dma function. any dma-related register bits should be left in their reset state for normal mcu operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) features mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 229 13.3 features features of the sci module include the following: full duplex operation standard mark/space non-return-to-zero (nrz) format programmable 8-bit or 9-bit character length separately enabled transmitter and receiver separate receiver and transmitter cpu interrupt requests two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection features of the infrared (ir) sub-module include the following: ir sub-module enable/disable for infrared sci or conventional sci on txd and rxd pins software selectable infrared modulation/demodulation (3/16, 1/16 or 1/32 width pulses) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 230 infrared serial communications interface module (irsci) motorola addr.register name bit 7654321bit 0 $0013 sci control register 1 (scc1) read: loops ensci 0 m wake ilty pen pty write: reset:00000000 $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset:uu000000 $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 sci status register 2 (scs2) read: bkf rpf write: reset:00000000 $0018 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) read: cks 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 $001a sci infrared control register (scircr) read: r 000 r tnp1 tnp0 iren write: reset:00000000 = unimplemented r = reserved u = unaffected figure 13-1. irsci i/o registers summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) pin name conventions mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 231 13.4 pin name conventions the generic names of the irsci i/o pins are: rxd (receive data) txd (transmit data) irsci i/o (input/output) lines are implemented by sharing parallel i/o port pins. the full name of an irsci input or output reflects the name of the shared port pin. table 13-1 shows the full names and the generic names of the irsci i/o pins. the generic pin names appear in the text of this section. 13.5 irsci module overview the irsci consists of a serial communications interface (sci) and a infrared interface sub-module as shown in figure 13-2 . figure 13-2. irsci block diagram the sci module provides serial data transmission and reception, with a programmable baud rate clock based on the bus clock or the cgmxclk. table 13-1. pin name conventions generic pin names: rxd txd full pin names: ptb1/rxd ptb0/txd txd infrared sub-module sci_txd sci_r32xclk sci_r16xclk serial cgmxclk bus clock internal bus communications interface module (sci) rxd sci_rxd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 232 infrared serial communications interface module (irsci) motorola the infrared sub-module receives two clock sources from the sci module: sci_r16xclk and sci_r32xclk. both reference clocks are used to generate the narrow pulses during data transmission. the sci_r16xclk and sci_r32xclk are internal clocks with frequencies that are 16 and 32 times the baud rate respectively. both sci_r16xclk and sci_r32xclk clocks are used for transmitting data. the sci_r16xclk clock is used only for receiving data. note: for proper sci function (transmit or receive), the bus clock must be programmed to at least 32 times that of the selected baud rate. when the infrared sub-module is disabled, signals on the txd and rxd pins pass through unchanged to the sci module. 13.6 infrared functional description figure 13-3 shows the structure of the infrared sub-module. figure 13-3. infrared sub-module diagram the infrared sub-module provides the capability of transmitting narrow pulses to an infrared led and receiving narrow pulses and transforming them to serial bits, which are sent to the sci module. the infrared sub- module receives two clocks from the sci. one of these two clocks is selected as the base clock to generate the 3/16, 1/16, or 1/32 bit width narrow pulses during transmission. sci_r16xclk transmit encoder receive decoder mux mux txd rxd ir_txd tnp[1:0] sci_txd ir_rxd sci_rxd iren sci_r32xclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) infrared functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 233 the sub-module consists of two main blocks: the transmit encoder and the receive decoder. when transmitting data, the sci data stream is encoded by the infrared sub-module. for every "0" bit, a narrow "low" pulse is transmitted; no pulse is transmitted for "1" bits. when receiving data, the infrared pulses should be detected using an infrared photo diode for conversion to cmos voltage levels before connecting to the rxd pin for the infrared decoder. the sci data stream is reconstructed by stretching the "0" pulses. 13.6.1 infrared transmit encoder the infrared transmit encoder converts the "0" bits in the serial data stream from the sci module to narrow "low" pulses, to the txd pin. the narrow pulse is sent with a duration of 1/32, 1/16, or 3/16 of a data bit width . when two consecutive zeros are sent, the two consecutive narrow pulses will be separated by a time equal to a data bit width. figure 13-4. infrared sci data example 13.6.2 infrared receive decoder the infrared receive decoder converts low narrow pulses from the rxd pin to standard sci data bits. the reference clock, sci_r16xclk, clocks a four bit internal counter which counts from 0 to 15. an incoming pulse starts the internal counter and a "0" is sent out to the ir_rxd output. subsequent incoming pulses are ignored when the counter count is between 0 and 7; ir_rxd remains "0". once the counter passes 7, an incoming pulse will reset the counter; ir_rxd remains "0". when the counter reaches 15, the ir_rxd output returns to "1", the counter stops and waits for further pulses. a pulse is interpreted as jitter if it arrives shortly after the counter reaches 15; ir_rxd remains "1". sci data infrared sci data data bit width determined by baud rate pulse width = 1/32, 1/16, or 3/16 data bit width f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 234 infrared serial communications interface module (irsci) motorola 13.7 sci functional description figure 13-5 shows the structure of the sci. figure 13-5. sci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 dmate orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register dma interrupt control transmitter interrupt control receiver interrupt control error interrupt control control dmare ensci loops ensci internal bus loops 16 baud rate generator cgmxclk bus clock a b sl x sl = 0 => x = a sl = 1 => x = b cks sci_txd sci_rxd sci_r32xclk sci_r16xclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) sci functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 235 the sci allows full-duplex, asynchronous, nrz serial communication between the mcu and remote devices, including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. note: for sci operations, the ir sub-module is transparent to the sci module. data at going out of the sci transmitter and data going into the sci receiver is always in sci format. it makes no difference to the sci module whether the ir sub-module is enabled or disabled. note: this sci module is a standard hc08 sci module with the following modifications: a control bit, cks, is added to the sci baud rate control register to select between two input clocks for baud rate clock generation the txinv bit is removed from the sci control register 1 13.7.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 13-6 . figure 13-6. sci data formats bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format bit m in scc1 clear start bit bit 0 next stop bit start bit 9-bit data format bit m in scc1 set bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity bit parity bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 236 infrared serial communications interface module (irsci) motorola 13.7.2 transmitter figure 13-7 shows the structure of the sci transmitter. the baud rate clock source for the sci can be selected by the cks bit, in the sci baud rate register (see 13.11.7 sci baud rate register (scbr) ). figure 13-7. sci transmitter dmate scte pen pty h876543210l 11-bit transmit stop start t8 dmate scte sctie tcie sbk tc parity generation msb sci data register load from scdr shift enable preamble all 1s break all 0s transmitter control logic shift register dmate tc sctie tcie scte transmitter cpu interrupt request transmitter dma service request m ensci loops te internal bus pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider 16 sctie sci_txd cgmxclk bus clock a b sl x sl = 0 => x = a sl = 1 => x = b cks f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) sci functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 237 13.7.2.1 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitting 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). 13.7.2.2 character transmission during an sci transmission, the transmit shift register shifts a character out to the txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. to initiate an sci transmission: 1. enable the sci by writing a logic 1 to the enable sci bit (ensci) in sci control register 1 (scc1). 2. enable the transmitter by writing a logic 1 to the transmitter enable bit (te) in sci control register 2 (scc2). 3. clear the sci transmitter empty bit by first reading sci status register 1 (scs1) and then writing to the scdr. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. after the preamble shifts out, control logic transfers the scdr data into the transmit shift register. a logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. a logic 1 stop bit goes into the most significant bit position. the sci transmitter empty bit, scte, in scs1 becomes set when the scdr transfers a byte to the transmit shift register. the scte bit indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter interrupt request. when the transmit shift register is not transmitting a character, the txd pin goes to the idle condition, logic 1. if at any time software clears the ensci bit in sci control register 1 (scc1), the transmitter and receiver relinquish control of the port pins. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 238 infrared serial communications interface module (irsci) motorola 13.7.2.3 break characters writing a logic 1 to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. the sci recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has the following effects on sci registers: sets the framing error bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci data register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits 13.7.2.4 idle characters an idle character contains all logic 1s and has no start, stop, or parity bit. idle character length depends on the m bit in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmission, the txd pin becomes idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) sci functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 239 note: when queueing an idle character, return the te bit to logic 1 before the stop bit of the current character shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to the scdr to be lost. toggle the te bit for a queued idle character when the scte bit becomes set and just before writing the next byte to the scdr. 13.7.2.5 transmitter interrupts the following conditions can generate cpu interrupt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. 13.7.3 receiver figure 13-8 shows the structure of the sci receiver. 13.7.3.1 character length the receiver can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bit data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 240 infrared serial communications interface module (irsci) motorola figure 13-8. sci receiver block diagram all 1s all 0s m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery dmare scrf or orie nf neie fe feie pe peie dmare scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request dma service request cpu interrupt request sci data register r8 dmare orie neie feie peie scrie ilie rwu scrf idle or nf fe pe internal bus pre- scaler baud divider 16 scp1 scp0 scr2 scr1 scr0 scrie dmare sci_rxd cgmxclk bus clock a b sl x sl = 0 => x = a sl = 1 => x = b cks f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) sci functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 241 13.7.3.2 character reception during an sci reception, the receive shift register shifts characters in from the rxd pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive shift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if the sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request. 13.7.3.3 data sampling the receiver samples the rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 13-9 ): after every start bit after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) figure 13-9. receiver data sampling rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb sci_rxd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 242 infrared serial communications interface module (irsci) motorola to locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 13-2 summarizes the results of the start bit verification samples. if start bit verification is not successful, the rt clock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 13-3 summarizes the results of the data bit samples. table 13-2. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 table 13-3. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) sci functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 243 note: the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verification, the noise flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 13-4 summarizes the results of the stop bit samples. 13.7.3.4 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. the fe flag is set at the same time that the scrf bit is set. a break character that has no stop bit also sets the fe bit. 13.7.3.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. table 13-4. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 244 infrared serial communications interface module (irsci) motorola as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. slow data tolerance figure 13-10 shows how much a slow received character can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 13-10. slow data for an 8-bit character, data sampling of the stop bit takes the receiver 9bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 13-10 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 13-10 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles + 3 rt cycles = 163 rt cycles. msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 ? 154 ------------------------- - 100 4.54% = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) sci functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 245 the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is fast data tolerance figure 13-11 shows how much a fast received character can be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still there for the stop bit data samples at rt8, rt9, and rt10. figure 13-11. fast data for an 8-bit character, data sampling of the stop bit takes the receiver 9bittimes 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 13-11 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 13-11 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. 170 163 ? 170 ------------------------- - 100 4.12% = idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ------------------------- - 100 3.90% = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 246 infrared serial communications interface module (irsci) motorola the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 13.7.3.6 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bit in scc1, either of two conditions on the rxd pin can bring the receiver out of the standby state: address mark ? an address mark is a logic 1 in the most significant bit position of a received character. when the wake bit is set, an address mark wakes the receiver from the standby state by clearing the rwu bit. the address mark also sets the sci receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. idle input line condition ? when the wake bit is clear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. note: clearing the wake bit after the rxd pin has been idle may cause the receiver to wake up immediately. 170 176 ? 170 ------------------------- - 100 3.53% = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) sci functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 247 13.7.3.7 receiver interrupts the following sources can generate cpu interrupt requests from the sci receiver: sci receiver full (scrf) ? the scrf bit in scs1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver interrupt request. setting the sci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. idle input (idle) ? the idle bit in scs1 indicates that 10 or 11 consecutive logic 1s shifted in from the rxd pin. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 13.7.3.8 error interrupts the following receiver error flags in scs1 can generate cpu interrupt requests: receiver overrun (or) ? the or bit indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. the previous character remains in the scdr, and the new character is lost. the overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate sci error cpu interrupt requests. framing error (fe) ? the fe bit in scs1 is set when a logic 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to generate sci error cpu interrupt requests. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 248 infrared serial communications interface module (irsci) motorola 13.8 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 13.8.1 wait mode the sci module remains active after the execution of a wait instruction. in wait mode, the sci module registers are not accessible by the cpu. any enabled cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. refer to 9.7 low-power modes for information on exiting wait mode. 13.8.2 stop mode the sci module is inactive after the execution of a stop instruction. the stop instruction does not affect sci register states. sci module operation resumes after an external interrupt. because the internal clock is inactive during stop mode, entering stop mode during an sci transmission or reception results in invalid data. refer to 9.7 low-power modes for information on exiting stop mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) sci during break module interrupts mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 249 13.9 sci during break module interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during interrupts generated by the break module. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 13.10 i/o signals the two irsci i/o pins are: ptb0/txd ? transmit data ptb1/rxd ? receive data 13.10.1 ptb0/txd (transmit data) the ptb0/txd pin is the serial data (standard or infrared) output from the sci transmitter. the irsci shares the ptb0/txd pin with port b. when the irsci is enabled, the ptb0/txd pin is an output regardless of the state of the ddrb0 bit in data direction register b (ddrb). txd pin has high current (15ma) sink capability when the ledb0 bit is set in the port b led control register ($000c). 13.10.2 ptb1/rxd (receive data) the ptb1/rxd pin is the serial data input to the irsci receiver. the irsci shares the ptb1/rxd pin with port b. when the irsci is enabled, the ptb1/rxd pin is an input regardless of the state of the ddrb1 bit in data direction register b (ddrb). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 250 infrared serial communications interface module (irsci) motorola table 13-5 shows a summary of i/o pin functions when the sci is enabled. 13.11 i/o registers the following i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr) sci infrared control register (scircr) table 13-5. sci pin functions (standard and infrared) scc1 [ensci] scircr [iren] scc2 [te] scc2 [re] txd pin rxd pin 1000 hi-z (1) input ignored (terminate externally) 1001 hi-z (1) input sampled, pin should idle high 1 0 1 0 output sci (idle high) input ignored (terminate externally) 1 0 1 1 output sci (idle high) input sampled, pin should idle high 1100 hi-z (1) input ignored (terminate externally) 1101 hi-z (1) input sampled, pin should idle high 1 1 1 0 output ir sci (idle high) input ignored (terminate externally) 1 1 1 1 output ir sci (idle high) input sampled, pin should idle high 0 x x x pins under port control (standard i/o port) notes : 1. after completion of transmission in progress. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 251 13.11.1 sci control register 1 sci control register: enables loop mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type loops ? loop mode select bit this read/write bit enables loop mode operation for the sci only. in loop mode the rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. the infrared encoder/decoder is not in the loop. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled address: $0013 bit 7654321bit 0 read: loops ensci 0 m wake ilty pen pty write: reset:00000000 figure 13-12. sci control register 1 (scc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 252 infrared serial communications interface module (irsci) motorola m ? mode (character length) bit this read/write bit determines whether sci characters are eight or nine bits long. (see table 13-6 .) the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup condition bit this read/write bit determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit determines when the sci starts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen ? parity enable bit this read/write bit enables the sci parity function. (see table 13-6 .) when enabled, the parity function inserts a parity bit in the most significant bit position. (see figure 13-6 .) reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 253 pty ? parity bit this read/write bit determines whether the sci generates and checks for odd parity or even parity. (see table 13-6 .) reset clears the pty bit. 1 = odd parity 0 = even parity note: changing the pty bit in the middle of a transmission or reception can generate a parity error. 13.11.2 sci control register 2 sci control register 2: enables the following cpu interrupt requests: ? enables the scte bit to generate transmitter cpu interrupt requests ? enables the tc bit to generate transmitter cpu interrupt requests ? enables the scrf bit to generate receiver cpu interrupt requests ? enables the idle bit to generate receiver cpu interrupt requests enables the transmitter enables the receiver enables sci wakeup transmits sci break characters table 13-6. character format selection control bits character format mpen:pty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 254 infrared serial communications interface module (irsci) motorola sctie ? sci transmit interrupt enable bit this read/write bit enables the scte bit to generate sci transmitter cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission complete interrupt enable bit this read/write bit enables the tc bit to generate sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests te ? transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the txd pin. if software clears the te bit, the transmitter completes any transmission in progress before the txd returns to the idle condition address: $0014 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 13-13. sci control register 2 (scc2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 255 (logic 1). clearing and then setting te during a transmission queues an idle character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note: writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note: writing to the re bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this read/write bit transmits a break character followed by a logic 1. the logic 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no logic 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note: do not toggle the sbk bit immediately after setting the scte bit. toggling sbk before the preamble begins causes the sci to send a break character instead of a preamble. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 256 infrared serial communications interface module (irsci) motorola 13.11.3 sci control register 3 sci control register 3: stores the ninth sci data bit received and the ninth sci data bit to be transmitted enables the following interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts ? parity error interrupts r8 ? received bit 8 when the sci is receiving 9-bit characters, r8 is the read-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other 8 bits. when the sci is receiving 8-bit characters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift register at the same time that the scdr is loaded into the transmit shift register. reset has no effect on the t8 bit. address: $0015 bit 7654321bit 0 read: r8 t8 dmare dmate orie neie feie peie write: reset:uu000000 = unimplemented u = unaffected figure 13-14. sci control register 3 (scc3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 257 dmare ? dma receive enable bit caution: the dma module is not included on this mcu. writing a logic 1 to dmare or dmate may adversely affect mcu performance. 1 = dma not enabled to service sci receiver dma service requests generated by the scrf bit (sci receiver cpu interrupt requests enabled) 0 = dma not enabled to service sci receiver dma service requests generated by the scrf bit (sci receiver cpu interrupt requests enabled) dmate ? dma transfer enable bit caution: the dma module is not included on this mcu. writing a logic 1 to dmare or dmate may adversely affect mcu performance. 1 = scte dma service requests enabled; scte cpu interrupt requests disabled 0 = scte dma service requests disabled; scte cpu interrupt requests enabled orie ? receiver overrun interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. reset clears orie. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt requests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = sci error cpu interrupt requests from ne bit enabled 0 = sci error cpu interrupt requests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 258 infrared serial communications interface module (irsci) motorola peie ? receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the parity error bit, pe. (see 13.11.4 sci status register 1 .) reset clears peie. 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt requests from pe bit disabled 13.11.4 sci status register 1 sci status register 1 contains flags to signal these conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? sci transmitter empty bit this clearable, read-only bit is set when the scdr transfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt request. in normal address: $0016 bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 13-15. sci status register 1 (scs1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 259 operation, clear the scte bit by reading scs1 with scte set and then writing to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc ? transmission complete bit this read-only bit is set when the scte bit is set, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is automatically cleared when data, preamble or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver cpu interrupt request. when the scrie bit in scc2 is set, scrf generates a cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an sci error cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit before an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or idle since the idle bit was cleared) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 260 infrared serial communications interface module (irsci) motorola or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the data in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an overrun to occur between reads of scs1 and scdr in the flag-clearing sequence. figure 13-16 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag- clearing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag- clearing routine can check the or bit in a second read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is also set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 261 figure 13-16. flag clearing sequence pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 262 infrared serial communications interface module (irsci) motorola 13.11.5 sci status register 2 (scs2) sci status register 2 contains flags to signal the following conditions: break character detected incoming data bkf ? break flag bit this clearable, read-only bit is set when the sci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set again only after logic 1s again appear on the rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected rpf ? reception in progress flag bit this read-only bit is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. polling rpf before disabling the sci module or entering stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $0017 bit 7654321bit 0 read: bkf rpf write: reset:00000000 = unimplemented figure 13-17. sci status register 2 (scs2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 263 13.11.6 sci data register (scdr) the sci data register is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the sci data register. r7/t7 ? r0/t0 ? receive/transmit data bits reading the scdr accesses the read-only received data bits, r7 ? r0. writing to the scdr writes the data to be transmitted, t7 ? t0. reset has no effect on scdr. note: do not use read/modify/write instructions on the sci data register. address: $0018 bit 7654321bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 13-18. sci data register (scdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 264 infrared serial communications interface module (irsci) motorola 13.11.7 sci baud rate register (scbr) the baud rate register selects the baud rate for both the receiver and the transmitter. cks ? baud clock input select this read/write bit selects the source clock for the baud rate generator. reset clears the cks bit, selecting cgmxclk. 1 = bus clock drives the baud rate generator 0 = cgmxclk drives the baud rate generator scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 13-7 . reset clears scp1 and scp0. scr2 ? scr0 ? sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 13-8 . reset clears scr2 ? scr0. address: $0019 bit 7654321bit 0 read: cks 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved figure 13-19. sci baud rate register (scbr) table 13-7. sci baud rate prescaling scp1 and scp0 prescaler divisor (pd) 00 1 01 3 10 4 11 13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 265 use this formula to calculate the sci baud rate: where: sci clock source = f bus or cgmxclk (selected by cks bit) pd = prescaler divisor bd = baud rate divisor table 13-9 shows the sci baud rates that can be generated with a 4.9152-mhz bus clock when f bus is selected as sci clock source. table 13-8. sci baud rate selection scr2, scr1, and scr0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate sci clock source 16 pd bd -------------------------------------------- - = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 266 infrared serial communications interface module (irsci) motorola table 13-9. sci baud rate selection examples scp1 and scp0 prescaler divisor (pd) scr2, scr1, and scr0 baud rate divisor (bd) baud rate (f bus = 4.9152 mhz) 00 1 000 1 ? 00 1 001 2 ? 00 1 010 4 76800 00 1 011 8 38400 00 1 100 16 19200 00 1 101 32 9600 00 1 110 64 4800 00 1 111 128 2400 01 3 000 1 ? 01 3 001 2 51200 01 3 010 4 25600 01 3 011 8 12800 01 3 100 16 6400 01 3 101 32 3200 01 3 110 64 1600 01 3 111 128 800 10 4 000 1 76800 10 4 001 2 38400 10 4 010 4 19200 10 4 011 8 9600 10 4 100 16 4800 10 4 101 32 2400 10 4 110 64 1200 10 4 111 128 600 11 13 000 1 23632 11 13 001 2 11816 11 13 010 4 5908 11 13 011 8 2954 11 13 100 16 1477 11 13 101 32 739 11 13 110 64 369 11 13 111 128 185 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications interface module (irsci) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola infrared serial communications interface module (irsci) 267 13.11.8 sci infrared control register the infrared control register contains the control bits for the infrared sub- module. enables the infrared sub-module selects the infrared transmitter narrow pulse width tnp1 and tnp0 ? transmitter narrow pulse bits these read/write bits select the infrared transmitter narrow pulse width as shown in table 13-10 . reset clears tnp1 and tnp0. iren ? infrared enable bit this read/write bit enables the infrared sub-module for encoding and decoding the sci data stream. when this bit is clear, the infrared sub- module is disabled. reset clears the iren bit. 1 = infrared sub-module enabled 0 = infrared sub-module disabled address: $001a bit 7654321bit 0 read: r 000 r tnp1 tnp0 iren write: reset:00000000 = unimplemented r = reserved figure 13-20. sci infrared control register (scircr) table 13-10. infrared narrow pulse selection tnp1 and tnp0 prescaler divisor (pd) 00 sci transmits a 3/16 narrow pulse 01 sci transmits a 1/16 narrow pulse 10 sci transmits a 1/32 narrow pulse 11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . infrared serial communications technical data mc68HC908LJ12 ? rev. 2.0 268 infrared serial communications interface module (irsci) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 269 technical data ? mc68HC908LJ12 section 14. serial peripheral interface module (spi) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 14.4 pin name conventions and i/o register addresses . . . . . . . 271 14.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 14.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 14.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 14.6 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 14.6.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . 275 14.6.2 transmission format when cpha = 0 . . . . . . . . . . . . . . . 276 14.6.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . 278 14.6.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . 279 14.7 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . 281 14.8 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 14.8.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 14.8.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 14.9 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 14.10 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.11 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 14.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 14.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 14.12 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .290 14.13 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 14.13.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . . . 291 14.13.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . . . 291 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 270 serial peripheral interface module (spi) motorola 14.13.3 spsck (serial clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 14.13.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14.13.5 cgnd (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 14.14 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14.14.1 spi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14.14.2 spi status and control register . . . . . . . . . . . . . . . . . . . .296 14.14.3 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 14.2 introduction this section describes the serial peripheral interface (spi) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 14.3 features features of the spi module include the following: full-duplex operation master and slave modes double-buffered operation with separate transmit and receive registers four master mode frequencies (maximum = bus frequency 2) maximum slave mode frequency = bus frequency serial clock with programmable polarity and phase two separately enabled interrupts: ? sprf (spi receiver full) ? spte (spi transmitter empty) mode fault error flag with cpu interrupt capability overflow error flag with cpu interrupt capability programmable wired-or mode i 2 c (inter-integrated circuit) compatibility i/o (input/output) port bit(s) software configurable with pullup device(s) if configured as input port bit(s) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) pin name conventions and i/o register addresses mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 271 14.4 pin name conventions and i/o register addresses the text that follows describes the spi. the spi i/o pin names are ss (slave select), spsck (spi serial clock), cgnd (clock ground), mosi (master out slave in), and miso (master in/slave out). the spi shares four i/o pins with four parallel i/o ports. the full names of the spi i/o pins are shown in table 14-1 . the generic pin names appear in the text that follows. figure 14-1 summarizes the spi i/o registers. = 14.5 functional description figure 14-2 shows the structure of the spi module. table 14-1. pin name conventions spi generic pin names: miso mosi ss spsck cgnd full spi pin names: spi ptd1/miso ptd2/mosi ptd0/ss ptd3/spsck v ss addr.register name bit 7654321bit 0 $0010 spi control register (spcr) read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0011 spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $0012 spi data register (spdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset = unimplemented r = reserved figure 14-1. spi i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 272 serial peripheral interface module (spi) motorola figure 14-2. spi module block diagram the spi module allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt- driven. the following paragraphs describe the operation of the spi module. transmitter cpu interrupt request reserved receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 cgmout 2 clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie r spe spwom sprf spte ovrf reserved m s pin control logic receive data register sptie spe internal bus from sim modfen errie control modf spmstr mosi miso spsck ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 273 14.5.1 master mode the spi operates in master mode when the spi master bit, spmstr, is set. note: configure the spi modules as master or slave before enabling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling the master spi. (see 14.14.1 spi control register .) only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the transmit data register. if the shift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte. the byte begins shifting out on the mosi pin under the control of the serial clock. (see figure 14-3 .) figure 14-3. full-duplex master-slave connections shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 274 serial peripheral interface module (spi) motorola the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. (see 14.14.2 spi status and control register .) through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the master ? s miso pin. the transmission ends when the receiver full bit, sprf, becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. writing to the spi data register clears the spte bit. 14.5.2 slave mode the spi operates in slave mode when the spmstr bit is clear. in slave mode, the spsck pin is the input for the serial clock from the master mcu. before a data transmission occurs, the ss pin of the slave spi must be at logic 0. ss must remain low until the transmission is complete. (see 14.8.2 mode fault error .) in a slave spi module, data enters the shift register under the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it transfers to the receive data register, and the sprf bit is set. to prevent an overflow condition, slave software then must read the receive data register before another full byte enters the shift register. the maximum frequency of the spsck for an spi configured as a slave is the bus clock speed (which is twice as fast as the fastest master spsck clock that can be generated). the frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) transmission formats mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 275 when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. otherwise, the byte already in the slave shift register shifts out on the miso pin. data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first edge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. (see 14.6 transmission formats .) note: spsck must be in the proper idle state before the slave is enabled to prevent spsck from appearing as a clock edge. 14.6 transmission formats during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock synchronizes shifting and sampling on the two serial data lines. a slave select line allows selection of an individual slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can optionally be used to indicate multiple- master bus contention. 14.6.1 clock phase and polarity controls software can select any of four combinations of serial clock (spsck) phase and polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no significant effect on the transmission format. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 276 serial peripheral interface module (spi) motorola the clock phase (cpha) control bit selects one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. note: before writing to the cpol bit or the cpha bit, disable the spi by clearing the spi enable bit (spe). 14.6.2 transmission format when cpha = 0 figure 14-4 shows an spi transmission in which cpha is logic 0. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see 14.8.2 mode fault error .) when cpha = 0, the first spsck edge is the msb capture strobe. therefore, the slave must begin driving its data before the first spsck edge, and a falling edge on the ss pin is used to start the slave data transmission. the slave ? s ss pin must be toggled back to high and then low again between each byte transmitted as shown in figure 14-5 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) transmission formats mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 277 figure 14-4. transmission format (cpha = 0) figure 14-5. cpha/ss timing when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the falling edge of ss . any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 278 serial peripheral interface module (spi) motorola 14.6.3 transmission format when cpha = 1 figure 14-6 shows an spi transmission in which cpha is logic 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see 14.8.2 mode fault error .) when cpha = 1, the master begins driving its mosi pin on the first spsck edge. therefore, the slave uses the first spsck edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferable in systems having only one master and only one slave driving the miso data line. figure 14-6. transmission format (cpha = 1) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) transmission formats mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 279 when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the first edge of spsck. any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission. 14.6.4 transmission initiation latency when the spi is configured as a master (spmstr = 1), writing to the spdr starts a transmission. cpha has no effect on the delay to the start of the transmission, but it does affect the initial state of the spsck signal. when cpha = 0, the spsck signal remains inactive for the first half of the first spsck cycle. when cpha = 1, the first spsck cycle begins with an edge on the spsck line from its inactive to its active level. the spi clock rate (selected by spr1:spr0) affects the delay from the write to spdr and the start of the spi transmission. (see figure 14-7 .) the internal spi clock in the master is a free-running derivative of the internal mcu clock. to conserve power, it is enabled only when both the spe and spmstr bits are set. spsck edges occur halfway through the low time of the internal mcu clock. since the spi clock is free-running, it is uncertain where the write to the spdr occurs relative to the slower spsck. this uncertainty causes the variation in the initiation delay shown in figure 14-7 . this delay is no longer than a single spi bit time. that is, the maximum delay is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 280 serial peripheral interface module (spi) motorola figure 14-7. transmission start delay (master) write to spdr initiation delay bus mosi spsck cpha = 1 spsck cpha = 0 spsck cycle number msb bit 6 12 clock write to spdr earliest latest spsck = internal clock 2; earliest latest 2 possible start points spsck = internal clock 8; 8 possible start points earliest latest spsck = internal clock 32; 32 possible start points earliest latest spsck = internal clock 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock ? ? ? initiation delay from write spdr to transfer begin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) queuing transmission data mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 281 14.7 queuing transmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. the spi transmitter empty flag (spte) indicates when the transmit data buffer is ready to accept new data. write to the transmit data register only when the spte bit is high. figure 14-8 shows the timing associated with doing back-to-back transmissions with the spi (spsck has cpha: cpol = 1:0). figure 14-8. sprf/spte cpu interrupt timing the transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer. also, if no new data is written to the data buffer, the last value contained in the shift register is the next data word to be transmitted. bit 3 mosi spsck spte write to spdr 1 cpu writes byte 2 to spdr, queueing byte 2 cpu writes byte 1 to spdr, clearing spte bit. byte 1 transfers from transmit data 3 1 2 2 3 5 register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set. cpha:cpol = 1:0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 282 serial peripheral interface module (spi) motorola for an idle master or idle slave that has no data loaded into its transmit buffer, the spte is set again no more than two bus cycles after the transmit buffer empties into the shift register. this allows the user to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until the transmission is completed. this implies that a back-to-back write to the transmit data register is not possible. the spte indicates when the next write can occur. 14.8 error conditions the following flags signal spi error conditions: overflow (ovrf) ? failing to read the spi data register before the next full byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read. ovrf is in the spi status and control register. mode fault error (modf) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the spi status and control register. 14.8.1 overflow error the overflow flag (ovrf) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. the bit 1 capture strobe occurs in the middle of spsck cycle 7. (see figure 14-4 and figure 14-6 .) if an overflow occurs, all data received after the overflow and before the ovrf bit is cleared does not transfer to the receive data register and does not set the spi receiver full bit (sprf). the unread data that transferred to the receive data register before the overflow occurred can still be read. therefore, an overflow error always indicates the loss of data. clear the overflow flag by reading the spi status and control register and then reading the spi data register. ovrf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) error conditions mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 283 interrupts share the same cpu interrupt vector. (see figure 14-11 .) it is not possible to enable modf or ovrf individually to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. if the cpu sprf interrupt is enabled and the ovrf interrupt is not, watch for an overflow condition. figure 14-9 shows how it is possible to miss an overflow. the first part of figure 14-9 shows how it is possible to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf bit can be set in between the time that spscr and spdr are read. figure 14-9. missed read of overflow condition in this case, an overflow can be missed easily. since no more sprf interrupts can be generated until this ovrf is serviced, it is not obvious that bytes are being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spscr following the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions can set the sprf bit. figure 14-10 illustrates this process. generally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is not cleared. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. spscr spdr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 284 serial peripheral interface module (spi) motorola figure 14-10. clearing sprf when ovrf interrupt is not enabled 14.8.2 mode fault error setting the spmstr bit selects master mode and configures the spsck and mosi pins as outputs and the miso pin as an input. clearing spmstr selects slave mode and configures the spsck and mosi pins as inputs and the miso pin as an output. the mode fault bit, modf, becomes set any time the state of the slave select pin, ss , is inconsistent with the mode selected by spmstr. to prevent spi pin contention and damage to the mcu, a mode fault error occurs if: the ss pin of a slave spi goes high during a transmission the ss pin of a master spi goes low at any time for the modf flag to be set, the mode fault error enable bit (modfen) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. spscr spdr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) error conditions mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 285 modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. (see figure 14-11 .) it is not possible to enable modf or ovrf individually to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. in a master spi with the mode fault enable bit (modfen) set, the mode fault flag (modf) is set if ss goes to logic 0. a mode fault in a master spi causes the following events to occur: if errie = 1, the spi generates an spi receiver/error cpu interrupt request. the spe bit is cleared. the spte bit is set. the spi state counter is cleared. the data direction register of the shared i/o port regains control of port drivers. note: to prevent bus contention with another master spi after a mode fault error, clear all spi bits of the data direction register of the shared i/o port before enabling the spi. when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once the incoming spsck goes back to its idle level following the shift of the eighth data bit. when cpha = 1, the transmission begins when the spsck leaves its idle level and ss is already low. the transmission continues until the spsck returns to its idle level following the shift of the last data bit. (see 14.6 transmission formats .) note: setting the modf flag does not clear the spmstr bit. the spmstr bit has no function when spe = 0. reading spmstr when modf = 1 shows the difference between a modf occurring when the spi is a master and when it is a slave. when cpha = 0, a modf occurs if a slave is selected (ss is at logic 0) and later unselected (ss is at logic 1) even if no spsck is sent to that f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 286 serial peripheral interface module (spi) motorola slave. this happens because ss at logic 0 indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later unselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), the modf bit generates an spi receiver/error cpu interrupt request if the errie bit is set. the modf bit does not clear the spe bit or reset the spi in any way. software can abort the spi transmission by clearing the spe bit of the slave. note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. to clear the modf flag, read the spscr with the modf bit set and then write to the spcr register. this entire clearing mechanism must occur with no modf condition existing or else the flag is not cleared. 14.9 interrupts four spi status flags can be enabled to generate cpu interrupt requests. table 14-2. spi interrupts flag request spte transmitter empty spi transmitter cpu interrupt request (sptie = 1, spe = 1) sprf receiver full spi receiver cpu interrupt request (sprie = 1) ovrf overflow spi receiver/error interrupt request (errie = 1) modf mode fault spi receiver/error interrupt request (errie = 1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) interrupts mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 287 reading the spi status and control register with sprf set and then reading the receive data register clears sprf. the clearing mechanism for the spte flag is always just a write to the transmit data register. the spi transmitter interrupt enable bit (sptie) enables the spte flag to generate transmitter cpu interrupt requests, provided that the spi is enabled (spe = 1). the spi receiver interrupt enable bit (sprie) enables the sprf bit to generate receiver cpu interrupt requests, regardless of the state of the spe bit. (see figure 14-11 .) the error interrupt enable bit (errie) enables both the modf and ovrf bits to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf bit is enabled by the errie bit to generate receiver/error cpu interrupt requests. figure 14-11. spi interrupt request generation spte sptie sprf sprie r errie modf ovrf spe cpu interrupt request cpu interrupt request not available spi transmitter not available spi receiver/error f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 288 serial peripheral interface module (spi) motorola the following sources in the spi status and control register can generate cpu interrupt requests: spi receiver full bit (sprf) ? the sprf bit becomes set every time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf generates an spi receiver/error cpu interrupt request. spi transmitter empty (spte) ? the spte bit becomes set every time a byte transfers from the transmit data register to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte generates an spte cpu interrupt request. 14.10 resetting the spi any system reset completely resets the spi. partial resets occur whenever the spi enable bit (spe) is low. whenever spe is low, the following occurs: the spte flag is set. any transmission currently in progress is aborted. the shift register is cleared. the spi state counter is cleared, making it ready for a new complete transmission. all the spi port logic is defaulted back to being general-purpose i/o. these items are reset only by a system reset: all control bits in the spcr register all control bits in the spscr register (modfen, errie, spr1, and spr0) the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe between transmissions without having to set all control bits again when spe is set back high for the next transmission. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) low-power modes mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 289 by not resetting the sprf, ovrf, and modf flags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing 0 to the spe bit. the spi can also be disabled by a mode fault occurring in an spi that was configured as a master with the modfen bit set. 14.11 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 14.11.1 wait mode the spi module remains active after the execution of a wait instruction. in wait mode the spi module registers are not accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. to exit wait mode when an overflow condition occurs, enable the ovrf bit to generate cpu interrupt requests by setting the error interrupt enable bit (errie). (see 14.9 interrupts .) 14.11.2 stop mode the spi module is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions. spi operation resumes after an external interrupt. if stop mode is exited by reset, any transfer in progress is aborted, and the spi is reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 290 serial peripheral interface module (spi) motorola 14.12 spi during break interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see section 9. system integration module (sim) .) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. since the spte bit cannot be cleared during a break with the bcfe bit cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. therefore, a write to the spdr in break mode with the bcfe bit cleared has no effect. 14.13 i/o signals the spi module has five i/o pins and shares four of them with a parallel i/o port. they are: miso ? data received mosi ? data transmitted spsck ? serial clock ss ? slave select cgnd ? clock ground (internally connected to v ss ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o signals mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 291 the spi has limited inter-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becomes an open-drain output when the spwom bit in the spi control register is set. in i 2 c communication, the mosi and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . 14.13.1 miso (master in/slave out) miso is one of the two spi module pins that transmits serial data. in full duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only when the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is logic 0 and its ss pin is at logic 0. to support a multiple- slave system, a logic 1 on the ss pin puts the miso pin in a high- impedance state. when enabled, the spi controls data direction of the miso pin regardless of the state of the data direction register of the shared i/o port. 14.13.2 mosi (master out/slave in) mosi is one of the two spi module pins that transmits serial data. in full- duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direction of the mosi pin regardless of the state of the data direction register of the shared i/o port. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 292 serial peripheral interface module (spi) motorola 14.13.3 spsck (serial clock) the serial clock synchronizes data transmission between master and slave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the clock input. in full-duplex operation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi controls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port. 14.13.4 ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. (see 14.6 transmission formats .) since it is used to indicate the start of a transmission, the ss must be toggled high and low between each byte transmitted for the cpha = 0 format. however, it can remain low between transmissions for the cpha = 1 format. see figure 14-12 . figure 14-12. cpha/ss timing when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. (see 14.14.2 spi status and control register .) note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high- impedance state. the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o signals mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 293 when an spi is configured as a master, the ss input can be used in conjunction with the modf flag to prevent multiple masters from driving mosi and spsck. (see 14.8.2 mode fault error .) for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shared i/o port. with modfen high, it is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the port data register. (see table 14-3 .) 14.13.5 cgnd (clock ground) cgnd is the ground return for the serial clock pin, spsck, and the ground for the port output buffers. it is internally connected to v ss as shown in table 14-1 . table 14-3. spi configuration spe spmstr modfen spi configuration state of ss logic 0 x (1) x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi note 1. x = don ? t care f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 294 serial peripheral interface module (spi) motorola 14.14 i/o registers three registers control and monitor spi operation: spi control register (spcr) spi status and control register (spscr) spi data register (spdr) 14.14.1 spi control register the spi control register: enables spi module interrupt requests configures the spi module as master or slave selects serial clock polarity and phase configures the spsck, mosi, and miso pins as open-drain outputs enables the spi module sprie ? spi receiver interrupt enable bit this read/write bit enables cpu interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the shift register to the receive data register. reset clears the sprie bit. 1 = sprf cpu interrupt requests enabled 0 = sprf cpu interrupt requests disabled address: $0010 bit 7654321bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 = unimplemented r = reserved figure 14-13. spi control register (spcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 295 spmstr ? spi master bit this read/write bit selects master mode operation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode cpol ? clock polarity bit this read/write bit determines the logic state of the spsck pin between transmissions. (see figure 14-4 and figure 14-6 .) to transmit data between spi modules, the spi modules must have identical cpol values. reset clears the cpol bit. cpha ? clock phase bit this read/write bit controls the timing relationship between the serial clock and spi data. (see figure 14-4 and figure 14-6 .) to transmit data between spi modules, the spi modules must have identical cpha values. when cpha = 0, the ss pin of the slave spi module must be set to logic 1 between bytes. (see figure 14-12 .) reset sets the cpha bit. spwom ? spi wired-or mode bit this read/write bit disables the pullup devices on pins spsck, mosi, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsck, mosi, and miso pins spe ? spi enable this read/write bit enables the spi module. clearing spe causes a partial reset of the spi. (see 14.10 resetting the spi .) reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie ? spi transmit interrupt enable this read/write bit enables cpu interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. reset clears the sptie bit. 1 = spte cpu interrupt requests enabled 0 = spte cpu interrupt requests disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 296 serial peripheral interface module (spi) motorola 14.14.2 spi status and control register the spi status and control register contains flags to signal these conditions: receive data register full failure to clear sprf bit before next byte is received (overflow error) inconsistent logic level on ss pin (mode fault error) transmit data register empty the spi status and control register also contains bits that perform these functions: enable error interrupts enable mode fault error detection select master spi baud rate sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the sprie bit in the spi control register is set also. during an sprf cpu interrupt, the cpu clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full address: $0011 bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 = unimplemented figure 14-14. spi status and control register (spscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 297 errie ? error interrupt enable bit this read/write bit enables the modf and ovrf bits to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests 0 = modf and ovrf cannot generate cpu interrupt requests ovrf ? overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. in an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the receive data register. reset clears the ovrf bit. 1 = overflow 0 = no overflow modf ? mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission with the modfen bit set. in a master spi, the modf flag is set if the ss pin goes low at any time with the modfen bit set. clear the modf bit by reading the spi status and control register (spscr) with modf set and then writing to the spi control register (spcr). reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte ? spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte cpu interrupt request if the sptie bit in the spi control register is set also. note: do not write to the spi data register unless the spte bit is high. during an spte cpu interrupt, the cpu clears the spte bit by writing to the transmit data register. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data register not empty f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 298 serial peripheral interface module (spi) motorola modfen ? mode fault enable bit this read/write bit, when set to 1, allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is low, then the ss pin is available as a general-purpose i/o. if the modfen bit is set, then this pin is not available as a general- purpose i/o. when the spi is enabled as a slave, the ss pin is not available as a general-purpose i/o regardless of the value of modfen. (see 14.13.4 ss (slave select) .) if the modfen bit is low, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. (see 14.8.2 mode fault error .) spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 14-4 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use this formula to calculate the spi baud rate: where: cgmout = base clock output of the clock generator module (cgm) bd = baud rate divisor table 14-4. spi master baud rate selection spr1 and spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 baud rate cgmout 2bd -------------------------- = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola serial peripheral interface module (spi) 299 14.14.3 spi data register the spi data register consists of the read-only receive data register and the write-only transmit data register. writing to the spi data register writes data into the transmit data register. reading the spi data register reads data from the receive data register. the transmit data and receive data registers are separate registers that can contain different values. (see figure 14-2 .) r7 ? r0/t7 ? t0 ? receive/transmit data bits note: do not use read-modify-write instructions on the spi data register since the register read is not the same as the register written. address: $0012 bit 7654321bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 14-15. spi data register (spdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data mc68HC908LJ12 ? rev. 2.0 300 serial peripheral interface module (spi) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola analog-to-digital converter (adc) 301 technical data ? mc68HC908LJ12 section 15. analog-to-digital converter (adc) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 15.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 15.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 15.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 15.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 15.4.5 result justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 15.4.6 monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 15.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 15.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 15.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 15.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 15.7.1 adc voltage in (v adin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 15.7.2 adc analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . 309 15.7.3 adc voltage reference high pin (v refh ). . . . . . . . . . . . . 309 15.7.4 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . 309 15.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 15.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . . 310 15.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 15.8.3 adc clock control register. . . . . . . . . . . . . . . . . . . . . . . . 314 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data mc68HC908LJ12 ? rev. 2.0 302 analog-to-digital converter (adc) motorola 15.2 introduction this section describes the analog-to-digital convert (adc). the adc is a 6-channel 10-bit linear successive approximation adc. 15.3 features features of the adc module include: six channels with multiplexed input high impedance buffered input linear successive approximation with monotonicity 10-bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock conversion result justification ? 8-bit truncated mode ? right justified mode ? left justified mode ? left justified sign mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola analog-to-digital converter (adc) 303 15.4 functional description the adc provides six pins for sampling external sources at pins pta4/adc0 ? pta7/adc3 and ptb6/adc4 ? ptb7/adc5. an analog multiplexer allows the single adc converter to select one of nine adc channels as adc voltage in (v adin ). v adin is converted by the successive approximation register-based analog-to-digital converter. when the conversion is completed, adc places the result in the adc data register, high and low byte (adrh and adrl), and sets a flag or generates an interrupt. figure 15-2 shows the structure of the adc module. 15.4.1 adc port i/o pins pta4 ? pta7 and ptb6 ? ptb7 are general-purpose i/o pins that are shared with the adc channels. the channel select bits, adch[4:0], define which adc channel/port pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o addr.register name bit 7654321bit 0 $003c adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $003d adc data register high (adrh) read: adx adx adx adx adx adx adx adx write:rrrrrrrr reset:00000000 $003e adc data register low (adrl) read: adx adx adx adx adx adx adx adx write:rrrrrrrr reset:00000000 $003f adc clock register (adclk) read: adiv2 adiv1 adiv0 adiclk mode1 mode0 00 write: r reset:00000100 = unimplemented r = reserved figure 15-1. adc i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data mc68HC908LJ12 ? rev. 2.0 304 analog-to-digital converter (adc) motorola logic and can be used as general-purpose i/o pins. writes to the port data register or data direction register will not have any affect on the port pin that is selected by the adc. read of a port pin which is in use by the adc will return the pin condition if the corresponding ddr bit is at logic 0. if the ddr bit is at logic 1, the value in the port data latch is read. figure 15-2. adc block diagram adc data registers internal data bus read ddrax/ddrbx write ddrax/ddrbx reset write ptax/ptbx read ptax/ptbx ptax/ptbx ddrax/ddrbx ptax/ptbx interrupt logic channel select adc clock generator conversion complete adc (v adin ) adc clock cgmxclk bus clock disable disable (6 channels) adiv[2:0] adiclk voltage in v refl v refh adch[4:0] adc0 ? adc5 coco aien adrh adrl 1.2v bandgap reference f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola analog-to-digital converter (adc) 305 15.4.2 voltage conversion when the input voltage to the adc equals v refh , the adc converts the signal to $3ff (full scale). if the input voltage equals v refl , the adc converts it to $000. input voltages between v refh and v refl are straight-line linear conversions. all other input voltages will result in $3ff if greater than v refh and $000 if less than v refl . note: input voltage should not exceed the analog supply voltages. 15.4.3 conversion time conversion starts after a write to the adscr. a conversion is between 16 and 17 adc clock cycles, therefore: the adc conversion time is determined by the clock source chosen and the divide ratio selected. the clock source is either the bus clock or cgmxclk and is selectable by the adiclk bit located in the adc clock register. the divide ratio is selected by the adiv[2:0] bits. for example, if a 4mhz cgmxclk is selected as the adc input clock source, with a divide-by-2 prescale, and the bus speed is set at 8mhz: note: the adc frequency must be between f adic minimum and f adic maximum to meet adc specifications. see 23.6 5.0v dc electrical characteristics . since an adc cycle may be comprised of several bus cycles (eight in the previous example) and the start of a conversion is initiated by a bus cycle write to the adscr, from zero to four additional bus cycles may occur before the start of the initial adc cycle. this results in a fractional adc cycle and is represented as the 17th cycle. 16 to17 adc cycles conversion time = adc frequency number of bus cycles = conversion time bus frequency 16 to 17 adc cycles conversion time = 4mhz 2 number of bus cycles = 8 s x 8mhz = 64 to 68 cycles = 8 to 8.5 s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data mc68HC908LJ12 ? rev. 2.0 306 analog-to-digital converter (adc) motorola 15.4.4 continuous conversion in the continuous conversion mode, the adc continuously converts the selected channel, filling the adc data register (adrh:adrl) with new data after each conversion. data from the previous conversion will be overwritten whether that data has been read or not. conversions will continue until the adco bit is cleared. the coco bit is set after each conversion and can be cleared by writing to the adc status and control register or reading of the adrl data register. 15.4.5 result justification the conversion result may be formatted in four different ways. left justified right justified left justified sign data mode 8-bit truncation all four of these modes are controlled using mode0 and mode1 bits located in the adc clock control register (adclk). left justification will place the eight most significant bits (msb) in the adc data register high (adrh). this may be useful if the result is to be treated as an 8-bit result where the least significant two bits, located in the adc data register low (adrl) can be ignored. however, adrl must be read after adrh or else the interlocking will prevent all new conversions from being stored. right justification will place only the two msbs in the corresponding adc data register high (adrh) and the eight lsb bits in adc data register low (adrl). this mode of operation typically is used when a 10-bit unsigned result is desired. left justified sign data mode is similar to left justified mode with one exception. the msb of the 10-bit result, ad9 located in adrh is complemented. this mode of operation is useful when a result, represented as a signed magnitude from mid-scale, is needed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola analog-to-digital converter (adc) 307 finally, 8-bit truncation mode will place the eight msbs in adc data register low (adrl). the two lsbs are dropped. this mode of operation is used when compatibility with 8-bit adc designs are required. no interlocking between adrh and adrl is present. note: quantization error is affected when only the most significant eight bits are used as a result. see figure 15-3 . figure 15-3. 8-bit truncation mode error 15.4.6 monotonicity the conversion process is monotonic and has no missing codes. ideal 10-bit characteristic with quantization = 1/2 ideal 8-bit characteristic with quantization = 1/2 10-bit truncated to 8-bit result when truncation is used, error from ideal 8-bit = 3/8 lsb due to non-ideal quantization. 000 001 002 003 004 005 006 007 008 009 00a 00b 000 001 002 003 8-bit result 10-bit result input voltage represented as 10-bit input voltage represented as 8-bit 1/2 2 1/2 4 1/2 6 1/2 8 1/2 1 1/2 3 1/2 5 1/2 7 1/2 9 1/2 1/2 2 1/2 1 1/2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data mc68HC908LJ12 ? rev. 2.0 308 analog-to-digital converter (adc) motorola 15.5 interrupts when the aien bit is set, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit is at logic 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. the interrupt vector is defined in table 2-1 . vector addresses . 15.6 low-power modes the stop and wait instructions put the mcu in low power- consumption standby modes. 15.6.1 wait mode the adc continues normal operation in wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting the adch[4:0] bits to logic 1 ? s before executing the wait instruction. 15.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode. allow one conversion cycle to stabilize the analog circuitry before attempting a new adc conversion after exiting stop mode. 15.7 i/o signals the adc module has nine channels, six channels are shared with port a and port c i/o pins; two channels are the adc voltage reference inputs, v refh and v refl ; and one channel is the 1.2v bandgap reference voltage. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o signals mc68HC908LJ12 ? rev. 2.0 technical data motorola analog-to-digital converter (adc) 309 15.7.1 adc voltage in (v adin ) v adin is the input voltage signal from one of the nine channels to the adc module. 15.7.2 adc analog power pin (v dda ) the adc analog portion uses v dda as its power pin. connect the v dda pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v dda for good results. note: route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 15.7.3 adc voltage reference high pin (v refh ) v refh is the power supply for setting the reference voltage v refh . connect the v refh pin to the same voltage potential as v dda . there will be a finite current associated with v refh (see section 23. electrical specifications ). note: route v refh carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 15.7.4 adc voltage reference low pin (v refl ) v refl is the lower reference supply for the adc. connect the v refl pin to the same voltage potential as v ssa . there will be a finite current associated with v refl (see section 23. electrical specifications ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data mc68HC908LJ12 ? rev. 2.0 310 analog-to-digital converter (adc) motorola 15.8 i/o registers these i/o registers control and monitor operation of the adc: adc status and control register, adscr adc data register, adrh:adrl adc clock register, adclk 15.8.1 adc status and control register this section describes the function of the adc status and control register (adscr). writing adscr aborts the current conversion and initiates a new conversion. coco ? conversions complete bit when the aien bit is a logic 0, the coco is a read-only bit which is set each time a conversion is completed. this bit is cleared whenever the adscr is written, or whenever the adc clock control register is written, or whenever the adc data register low, adrl, is read. if the aien bit is logic 1, the coco bit always read as logic 0, cpu to service the adc interrupt will be generated at the end if an adc conversion. reset clears the coco bit. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0)/cpu interrupt (aien=1) aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cleared when the data register, adr0, is read or the adscr is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled address: $003c read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 = unimplemented figure 15-4. adc status and control register (adscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola analog-to-digital converter (adc) 311 adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adc data register at the end of each conversion. only one conversion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] ? adc channel select bits adch[4:0] form a 5-bit field which is used to select one of the adc channels when not in auto-scan mode. the five channel select bits are detailed in table 15-1 . note: care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. note: recovery from the disabled state requires one conversion cycle to stabilize. table 15-1. mux channel select adch4 adch3 adch2 adch1 adch0 adc channel input select 00000 adc0 pta4 00001 adc1 pta5 00010 adc2 pta6 00011 adc3 pta7 00100 adc4 ptb6 00101 adc5 ptb7 00110 adc61.2v bandgap reference 00111 adc7 adc28 reserved 11100 11 1 0 1 adc29 v refh (see note 2) 11 1 1 0 adc30 v refl (see note 2) 11 1 1 1 adc powered-off notes: 1. if any reserved channels are selected, the resulting adc conversion will be unknown. 2. the voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the adc converter both in production test and for user applications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data mc68HC908LJ12 ? rev. 2.0 312 analog-to-digital converter (adc) motorola 15.8.2 adc data register the adc data register consist of a pair of 8-bit registers: high byte (adrh), and low byte (adrl). this pair form a 16-bit register to store the 10-bit adc result for the selected adc result justification mode. in 8-bit truncated mode, the adrl holds the eight most significant bits (msbs) of the 10-bit result. the adrl is updated each time an adc conversion completes. in 8-bit truncated mode, adrl contains no interlocking with adrh. (see figure 15-5 . adrh and adrl in 8-bit truncated mode .) in right justified mode the adrh holds the two msbs, and the adrl holds the eight least significant bits (lsbs), of the 10-bit result. adrh and adrl are updated each time a single channel adc conversion completes. reading adrh latches the contents of adrl. until adrl is read all subsequent adc results will be lost. (see figure 15-6 . adrh and adrl in right justified mode .) addr.register name bit 7654321bit 0 $003d adc data register high (adrh) read: 00000000 write:rrrrrrrr reset:00000000 $003e adc data register low (adrl) read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset:00000000 figure 15-5. adrh and adrl in 8-bit truncated mode addr.register name bit 7654321bit 0 $003d adc data register high (adrh) read: 000000ad9ad8 write:rrrrrrrr reset:00000000 $003e adc data register low (adrl) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write:rrrrrrrr reset:00000000 figure 15-6. adrh and adrl in right justified mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola analog-to-digital converter (adc) 313 in left justified mode the adrh holds the eight most significant bits (msbs), and the adrl holds the two least significant bits (lsbs), of the 10-bit result. the adrh and adrl are updated each time a single channel adc conversion completes. reading adrh latches the contents of adrl. until adrl is read all subsequent adc results will be lost. (see figure 15-7 . adrh and adrl in left justified mode .) in left justified sign mode the adrh holds the eight msbs with the msb complemented, and the adrl holds the two least significant bits (lsbs), of the 10-bit result. the adrh and adrl are updated each time a single channel adc conversion completes. reading adrh latches the contents of adrl. until adrl is read all subsequent adc results will be lost. (see figure 15-8 . adrh and adrl in left justified sign data mode .) addr.register name bit 7654321bit 0 $003d adc data register high (adrh) read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset:00000000 $003e adc data register low (adrl) read: ad1 ad0 000000 write:rrrrrrrr reset:00000000 figure 15-7. adrh and adrl in left justified mode addr.register name bit 7654321bit 0 $003d adc data register high (adrh) read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset:00000000 $003e adc data register low (adrl) read: ad1 ad0 000000 write:rrrrrrrr reset:00000000 figure 15-8. adrh and adrl in left justified sign data mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data mc68HC908LJ12 ? rev. 2.0 314 analog-to-digital converter (adc) motorola 15.8.3 adc clock control register the adc clock control register (adclk) selects the clock frequency for the adc. adiv[2:0] ? adc clock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit field which selects the divide ratio used by the adc to generate the internal adc clock. table 15-2 shows the available clock configurations. the adc clock should be set to between 32khz and 2mhz. adiclk ? adc input clock select bit adiclk selects either bus clock or cgmxclk as the input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. address: $003f read: adiv2 adiv1 adiv0 adiclk mode1 mode0 00 write: r reset:00000100 = unimplemented r = reserved figure 15-9. adc clock control register (adiclk) table 15-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x x adc input clock 16 x = don ? t care f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola analog-to-digital converter (adc) 315 if the external clock (cgmxclk) is equal to or greater than 1mhz, cgmxclk can be used as the clock source for the adc. if cgmxclk is less than 1mhz, use the pll-generated bus clock as the clock source. as long as the internal adc clock is at f adic , correct operation can be guaranteed. 1 = internal bus clock 0 = external clock, cgmxclk mode1 and mode0 ? modes of result justification mode1 and mode0 selects between four modes of operation. the manner in which the adc conversion results will be placed in the adc data registers is controlled by these modes of operation. reset returns right-justified mode. table 15-3. adc mode select mode1 mode0 adc clock rate 0 0 8-bit truncated mode 0 1 right justified mode 1 0 left justified mode 1 1 left justified sign data mode cgmxclk or bus frequency f adic = adiv[2:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data mc68HC908LJ12 ? rev. 2.0 316 analog-to-digital converter (adc) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola liquid crystal display driver (lcd) 317 technical data ? mc68HC908LJ12 section 16. liquid crystal display driver (lcd) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 16.4 pin name conventions and i/o register addresses . . . . . . . 318 16.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 16.5.1 lcd duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 16.5.2 lcd voltages (v lcd , v lcd1 , v lcd2 , v lcd3 ) . . . . . . . . . . . 323 16.5.3 lcd cycle frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 16.5.4 fast charge and low current . . . . . . . . . . . . . . . . . . . . . . 324 16.5.5 contrast control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 16.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 16.7.1 bp0 ? bp3 (backplane drivers) . . . . . . . . . . . . . . . . . . . . . .326 16.7.2 fp0 ? fp26 (frontplane drivers) . . . . . . . . . . . . . . . . . . . . . 328 16.8 seven segment display connection . . . . . . . . . . . . . . . . . . .332 16.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.9.1 lcd control register (lcdcr) . . . . . . . . . . . . . . . . . . . . . 335 16.9.2 lcd clock register (lcdclk) . . . . . . . . . . . . . . . . . . . . . 337 16.9.3 lcd data registers (ldat1 ? ldat14) . . . . . . . . . . . . . . . 339 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) technical data mc68HC908LJ12 ? rev. 2.0 318 liquid crystal display driver (lcd) motorola 16.2 introduction this section describes the liquid crystal display (lcd) driver module. the lcd driver module can drive a maximum of 27 frontplanes and 4 backplanes, depending on the lcd duty selected. 16.3 features features of the lcd driver module include the following: software programmable driver segment configurations: ? 26 frontplanes 4 backplanes (104 segments) ? 27 frontplanes 3 backplanes (81 segments) ? 27 frontplanes 1 backplane (27 segments) lcd bias voltages generated by internal resistor ladder software programmable contrast control 16.4 pin name conventions and i/o register addresses three dedicated i/o pins are for the backplanes, bp0 ? bp2, eighteen dedicated i/o pins are for the frontplanes, fp1 ? fp18, and the eight frontplanes, fp19 ? fp26, are shared with port c pins. fp0 and bp3 shares the same pin and configured by the duty[1:0] bits in the lcd clock register. the full names of the lcd output pins are shown in table 16-1 . the generic pin names appear in the text that follows. table 16-1. pin name conventions lcd generic pin name full mcu pin name pin selected for lcd function by: fp0/bp3 fp0/bp3 ? bp0 ? bp2 bp0 ? bp2 ? fp1 ? fp18 fp1 ? fp18 ? fp19 ? fp22 ptc0/fp19 ? ptc3/fp22 pcel in config2 fp23 ? fp26 ptc4/fp23 ? ptc7/fp26 pceh in config2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) pin name conventions and i/o register addresses mc68HC908LJ12 ? rev. 2.0 technical data motorola liquid crystal display driver (lcd) 319 addr.register name bit 7654321bit 0 $004f lcd clock register (lcdclk) read: 0 fcctl1 fcctl0 duty1 duty0 lclk2 lclk1 lclk0 write: reset:00000000 $0051 lcd control register (lcdcr) read: lcde 0 fc lc lccon3 lccon2 lccon1 lccon0 write: reset:00000000 $0052 lcd data register 1 (ldat1) read: f1b3 f1b2 f1b1 f1b0 f0b3 f0b2 f0b1 f0b0 write: reset:uuuuuuuu $0053 lcd data register 2 (ldat2) read: f3b3 f3b2 f3b1 f3b0 f2b3 f2b2 f2b1 f2b0 write: reset:uuuuuuuu $0054 lcd data register 3 (ldat3) read: f5b3 f5b2 f5b1 f5b0 f4b3 f4b2 f4b1 f4b0 write: reset:uuuuuuuu $0055 lcd data register 4 (ldat4) read: f7b3 f7b2 f7b1 f7b0 f6b3 f6b2 f6b1 f6b0 write: reset:uuuuuuuu $0056 lcd data register 5 (ldat5) read: f9b3 f9b2 f9b1 f9b0 f8b3 f8b2 f8b1 f8b0 write: reset:uuuuuuuu $0057 lcd data register 6 (ldat6) read: f11b3 f11b2 f11b1 f11b0 f10b3 f10b2 f10b1 f10b0 write: reset:uuuuuuuu $0058 lcd data register 7 (ldat7) read: f13b3 f13b2 f13b1 f13b0 f12b3 f12b2 f12b1 f12b0 write: reset:uuuuuuuu $0059 lcd data register 8 (ldat8) read: f15b3 f15b2 f15b1 f15b0 f14b3 f14b2 f14b1 f14b0 write: reset:uuuuuuuu u = unaffected = unimplemented figure 16-1. lcd i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) technical data mc68HC908LJ12 ? rev. 2.0 320 liquid crystal display driver (lcd) motorola 16.5 functional description figure 16-2 shows a block diagram of the lcd driver module, and figure 16-3 shows a simplified schematic of the lcd system. the lcd driver module uses a 1/3 biasing method. the lcd power is supplied by mcu power supply v dd . voltages v lcd1 , v lcd2 , and v lcd3 are generated by an internal resistor ladder. the lcd data registers, ldat1 ? ldat14, control the lcd segments ? on/off, with each data register controlling two frontplanes. when a logic 1 is written to a fxbx bit in the data register, the corresponding frontplane-backplane segment will turn on. when a logic 0 is written, the the segment will turn off. $005a lcd data register 9 (ldat9) read: f17b3 f17b2 f17b1 f17b0 f16b3 f16b2 f16b1 f16b0 write: reset:uuuuuuuu $005b lcd data register 10 (ldat10) read: f19b3 f19b2 f19b1 f19b0 f18b3 f18b2 f18b1 f18b0 write: reset:uuuuuuuu $005c lcd data register 11 (ldat11) read: f21b3 f21b2 f21b1 f21b0 f20b3 f20b2 f20b1 f20b0 write: reset:uuuuuuuu $005d lcd data register 12 (ldat12) read: f23b3 f23b2 f23b1 f23b0 f22b3 f22b2 f22b1 f22b0 write: reset:uuuuuuuu $005e lcd data register 13 (ldat13) read: f25b3 f25b2 f25b1 f25b0 f24b3 f24b2 f24b1 f24b0 write: reset:uuuuuuuu $005f lcd data register 14 (ldat14) read: f26b3 f26b2 f26b1 f26b0 write: reset:uuuuuuuu u = unaffected = unimplemented figure 16-1. lcd i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola liquid crystal display driver (lcd) 321 when the lcd driver module is disabled (lcde = 0), the lcd display will be off, all backplane and frontplane drivers have the same potential as v dd . the resistor ladder is disconnected from v dd to reduce power consumption. figure 16-2. lcd block diagram 16.5.1 lcd duty the setting of the lcd output waveform duty is dependent on the number of backplane drivers required. three lcd duties are available: static duty ? bp0 is used only 1/3 duty ? bp0, bp1, and bp3 are used 1/4 duty ? bp0, bp1, bp2, and bp3 are used when the lcd driver module is enabled the backplane waveforms for the selected duty are driven out of the backplane pins. the backplane waveforms are periodic and are shown are shown in figure 16-6 , figure 16-5 , and figure 16-7 . lcd frontplane driver and data latch port-c logic backplane driver lcde (lcdc) state control 1/4 1/3 1/3 1/4 1/1 ptc7/fp26 ptc6/fp25 ptc5/fp24 ptc4/fp23 ptc3/fp22 ptc2/fp21 ptc1/fp20 ptc0/fp19 fp5 fp6 fp7 fp8 fp9 fp10 fp11 fp12 fp13 fp14 fp15 fp16 fp17 fp18 bp0 bp1 bp2 fp0/bp3 fp1 fp2 fp3 fp4 internal bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) technical data mc68HC908LJ12 ? rev. 2.0 322 liquid crystal display driver (lcd) motorola figure 16-3. simplified lcd schematic (1/3 duty, 1/3 bias) lcd fp0 fp1 fp24 bp0 bp1 bp2 r fp r fp r fp r bp r bp r bp v lcd (from v dd ) v lcd1 v lcd2 v lcd3 v bias r lcd r lcd r lcd v r v lcd lccon[3:0] bias control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola liquid crystal display driver (lcd) 323 16.5.2 lcd voltages (v lcd, v lcd1, v lcd2 , v lcd3 ) the voltage v lcd is connected directly to v dd . v lcd1 , v lcd2 , and v lcd3 are internal bias voltages for the lcd driver waveforms. they are derived from v lcd using a resistor ladder (see figure 16-3 ). the relative potential of the lcd voltages are: v lcd = v dd v lcd1 = 2/3 (v lcd ? v bias ) v lcd2 = 1/3 (v lcd ? v bias ) v lcd3 = v bias the v lcd3 bias voltage, v bias , is controlled by the lcd contrast control bits, lccon[2:0]. 16.5.3 lcd cycle frame the lcd driver module uses the cgmxclk (see section 7. oscillator (osc) ) as the input reference clock. this clock is divided to produce the lcd waveform base clock, lcdclk, by configuring the lclk[2:0] bits in the lcd clock register. the lcdclk clocks the backplane and the frontplane output waveforms. the lcd cycle frame is determined by the equation: for example, for 1/3 duty and 256hz waveform base clock: lcd cycle frame = lcd waveform base clock duty 1 lcd cycle frame = 256 (1/3) 1 = 11.72 ms f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) technical data mc68HC908LJ12 ? rev. 2.0 324 liquid crystal display driver (lcd) motorola 16.5.4 fast charge and low current the default value for each of the bias resistors (see figure 16-3 ), r lcd , in the resistor ladder is approximately 37k ? at v lcd = 3v. the relatively high current drain through the 37k ? resistor ladder may not be suitable for some lcd panel connections. lowering this current is possible by setting the lc bit in the lcd control register, switching the r lcd value to 146k ? . although the lower current drain is desirable, but in some lcd panel connections, the higher current is required to drive the capacitive load of the lcd panel. in most cases, the higher current is only required when the lcd waveforms change state (the rising and falling edges in the lcd output waveforms). the fast charge option is designed to have the high current for the switching and the low current for the steady state. setting the fc bit in the lcd control register selects the fast charge option. the r lcd value is set to 37k ? (for high current) for a fraction of time for each lcd waveform switching edge, and then back to 146k ? for the steady state period. the duration of the fast charge time is set by configuring the fcctl[1:0] bits in the lcd clock register, and can be lcdclk/32, lcdclk/64, or lcdclk/128. figure 16-4 shows the fast charge clock relative to the bp0 waveform. figure 16-4. fast charge timing lcd waveform fast charge clock lcdclk high current selected before switching edge, period is defined by fcctl[1:0] example: bp0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) low-power modes mc68HC908LJ12 ? rev. 2.0 technical data motorola liquid crystal display driver (lcd) 325 16.5.5 contrast control the contrast of the connected lcd panel can be adjusted by configuring the lccon[3:0] bits in the lcd control register. the lccon[3:0] bits provide a 16-step contrast control, which adjusts the bias voltage in the resistor ladder for lcd voltage v lcd3 . the relative voltages, v lcd1 and v lcd2 , are altered according. for example, setting lccon[3:0] = $f, the relative panel potential voltage (v lcd ? v lcd3 ) is reduced from maximum 3.3v to approximate 2.45v. 16.6 low-power modes the stop and wait instructions put the mcu in low power- consumption standby modes. 16.6.1 wait mode the lcd driver module continues normal operation in wait mode. if the lcd is not required in wait mode, power down the lcd module by clearing the lcde bit before executing the wait instruction. 16.6.2 stop mode for continuous lcd module operation in stop mode, the oscillator stop mode enable bit (stop_xclken in config2 register) must be set before executing the stop instruction. when stop_xclken is set, cgmxclk continues to drive the lcd module. if stop_xclken bit is cleared, the lcd module is inactive after the execution of a stop instruction. the stop instruction does not affect lcd register states. lcd module operation resumes after an external interrupt. to further reduce power consumption, the lcd module should be powered-down by clearing the lcde bit before executing the stop instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) technical data mc68HC908LJ12 ? rev. 2.0 326 liquid crystal display driver (lcd) motorola 16.7 i/o signals the lcd driver module has thirty (30) output pins and shares eight of them with port c i/o pins. fp0/bp3 (multiplexed; selected as fp0 or bp3 by duty[1:0]) bp0 ? bp2 fp1 ? fp26 (fp19 ? fp26 shared with port c) 16.7.1 bp0 ? bp3 (backplane drivers) bp0 ? bp3 are the backplane driver output pins. these are connected to the backplane of the lcd panel. depending on the lcd duty selected, the voltage waveforms in figure 16-6 , figure 16-5 , and figure 16-7 appear on the backplane pins. bp3 pin is only used when 1/4 duty is selected. the pin becomes fp0 for static and 1/3 duty operations. figure 16-5. 1/3 duty lcd backplane driver waveforms 1frame duty = 1/3 bp0 v lcd v lcd1 v lcd3 v lcd v lcd2 v lcd3 v lcd v lcd1 v lcd2 v lcd3 v lcd2 v lcd1 bp1 bp2 1. bp3 is not used. 2. at 1/3 duty, 1frame has three times the cycle of lcd waveform base clock. notes: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) i/o signals mc68HC908LJ12 ? rev. 2.0 technical data motorola liquid crystal display driver (lcd) 327 figure 16-6. static lcd backplane driver waveform figure 16-7. 1/4 duty lcd backplane driver waveforms 1frame duty = static bp0 v lcd v lcd1 v lcd3 v lcd2 1. bp1, bp2, and bp3 are not used. 2. at static duty, 1frame is equal to the cycle of lcd waveform base clock. notes: 1frame duty = 1/4 bp0 v lcd v lcd1 v lcd3 v lcd v lcd2 v lcd3 v lcd v lcd1 v lcd2 v lcd3 v lcd v lcd1 v lcd2 v lcd1 v lcd2 v lcd3 bp1 bp2 bp3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) technical data mc68HC908LJ12 ? rev. 2.0 328 liquid crystal display driver (lcd) motorola 16.7.2 fp0 ? fp26 (frontplane drivers) fp0 ? fp26 are the frontplane driver output pins. these are connected to the frontplane of the lcd panel. depending on lcd duty selected and the contents in the lcd data registers, the voltage waveforms in figure 16-8 , figure 16-9 , and figure 16-10 appear on the frontplane pins. fp19 ? fp26 are shared with port c i/o pins. these pins are configured for standard i/o or lcd use by the pcel and pceh bits in config2 register. figure 16-8. static lcd frontplane driver waveforms duty = static v lcd v lcd2 v lcd3 v lcd1 v lcd v lcd1 v lcd3 v lcd2 1 fxb0 ? ? ? 0 fxb0 ? ? ? data latch: 1 = on, 0 = off 1frame fpx output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) i/o signals mc68HC908LJ12 ? rev. 2.0 technical data motorola liquid crystal display driver (lcd) 329 . figure 16-9. 1/3 duty lcd frontplane driver waveforms duty = 1/3 data latch: 1 = on, 0 = off v lcd v lcd2 v lcd3 v lcd v lcd1 v lcd2 v lcd3 v lcd1 v lcd v lcd1 v lcd3 v lcd2 v lcd v lcd1 v lcd2 v lcd3 v lcd v lcd1 v lcd2 v lcd3 v lcd v lcd1 v lcd2 v lcd3 v lcd v lcd1 v lcd2 v lcd3 v lcd v lcd1 v lcd2 v lcd3 0 fxb0 0 fxb1 0 fxb2 ? 1 fxb0 0 fxb1 0 fxb2 ? 0 fxb0 0 fxb1 1 fxb2 ? 0 fxb0 1 fxb1 0 fxb2 ? 1 fxb0 1 fxb1 0 fxb2 ? 0 fxb0 1 fxb1 1 fxb2 ? 1 fxb0 0 fxb1 1 fxb2 ? 1 fxb0 1 fxb1 1 fxb2 ? fpx output 1frame f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) technical data mc68HC908LJ12 ? rev. 2.0 330 liquid crystal display driver (lcd) motorola figure 16-10. 1/4 duty lcd frontplane driver waveforms v lcd v lcd1 v lcd3 v lcd2 duty = 1/4 data latch: 1 = on, 0 = off fpx output 0 fxb0 0 fxb1 0 fxb2 0 fxb3 1 fxb0 0 fxb1 0 fxb2 0 fxb3 0 fxb0 1 fxb1 0 fxb2 0 fxb3 1 fxb0 1 fxb1 0 fxb2 0 fxb3 0 fxb0 0 fxb1 1 fxb2 0 fxb3 1 fxb0 0 fxb1 1 fxb2 0 fxb3 0 fxb0 1 fxb1 1 fxb2 0 fxb3 1 fxb0 1 fxb1 1 fxb2 0 fxb3 1frame f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) i/o signals mc68HC908LJ12 ? rev. 2.0 technical data motorola liquid crystal display driver (lcd) 331 figure 16-11. 1/4 duty lcd frontplane driver waveforms (continued) v lcd v lcd1 v lcd3 v lcd2 duty = 1/4 data latch: 1 = on, 0 = off fpx output 0 fxb0 0 fxb1 0 fxb2 1 fxb3 1 fxb0 0 fxb1 0 fxb2 1 fxb3 0 fxb0 1 fxb1 0 fxb2 1 fxb3 1 fxb0 1 fxb1 0 fxb2 1 fxb3 0 fxb0 0 fxb1 1 fxb2 1 fxb3 1 fxb0 0 fxb1 1 fxb2 1 fxb3 0 fxb0 1 fxb1 1 fxb2 1 fxb3 1 fxb0 1 fxb1 1 fxb2 1 fxb3 1frame f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) technical data mc68HC908LJ12 ? rev. 2.0 332 liquid crystal display driver (lcd) motorola 16.8 seven segment display connection the following shows an example for connecting a 7-segment lcd display to the lcd driver. the example uses 1/3 duty cycle, with pins bp0, bp1, bp2, fp0, fp1, and fp2 connected as shown in figure 16-12 . the output waveforms are shown in figure 16-13 . figure 16-12. 7-segment display example fp connection bp connection a f e b c g d bp0 ( a , b commoned) bp1 ( c , f , g commoned) bp2 ( d , e commoned) a f e b c g d fp2 the segment assignments for each bit in the data registers are: to display the character "4": ldat1 = x010x01x, ldat2 = xxxxxx11 a g d ? ? f e ? fp0 ? ? ? ? b c ? ? fp1 0 1 0 x x 1 0 x x x x x 1 1 x x fp0 ( e , f commoned) fp1 ( a , d , g commoned) fp2 ( b , c commoned) f0b0 f0b1 f0b2 f0b3 f1b0 f1b1 f1b2 f1b3 ldat1 $0052 ldat2 $0053 f2b0 f2b1 f2b2 f2b3 f3b0 f3b1 f3b2 f3b3 ldat1 $0052 ldat2 $0053 a f e b c g d x = don ? t care f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) seven segment display connection mc68HC908LJ12 ? rev. 2.0 technical data motorola liquid crystal display driver (lcd) 333 figure 16-13. bp0?bp2 and fp0?fp2 output waveforms for 7-segment display example duty = 1/3 v lcd v lcd1 v lcd2 v lcd3 v lcd v lcd1 v lcd2 v lcd3 1frame bp0 v lcd v lcd1 v lcd3 v lcd v lcd2 v lcd3 v lcd v lcd1 v lcd2 v lcd3 v lcd2 v lcd1 bp1 bp2 v lcd v lcd1 v lcd2 v lcd3 fp0 fp1 fp2 0 f1b0 1 f1b1 0 f1b2 ? 1 f2b0 1 f2b1 0 f2b2 ? 0 f0b0 1 f0b1 0 f0b2 ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) technical data mc68HC908LJ12 ? rev. 2.0 334 liquid crystal display driver (lcd) motorola the voltage waveform across the "f" segment of the lcd (between bp1 and fp0) is illustrated in figure 16-14 . as shown in the waveform, the voltage peaks reach the lcd-on voltage, v lcd , therefore, the segment will be on. figure 16-14. "f" segment voltage waveform the voltage waveform across the "e" segment of the lcd (between bp2 and fp0) is illustrated in figure 16-15 . as shown in the waveform, the voltage peaks do not reach the lcd-on voltage, v lcd , therefore, the segment will be off. figure 16-15. "e" segment voltage waveform bp1 ? fp0 +v lcd +v lcd1 +v lcd2 ? v lcd2 ? v lcd1 ? v lcd 0 +v lcd1 +v lcd2 ? v lcd2 ? v lcd1 ? v lcd +v lcd 0 bp2 ? fp0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola liquid crystal display driver (lcd) 335 16.9 i/o registers sixteen (16) registers control lcd driver module operation: lcd control register (lcdcr) lcd clock register (lcdclk) lcd data registers (ldat1 ? ldat14) 16.9.1 lcd control register (lcdcr) the lcd control register (lcdcr): enables the lcd driver module selects bias resistor value and fast-charge control selects lcd contrast lcde ? lcd enable this read/write bit enables the lcd driver module; the backplane and frontplane drive lcd waveforms out of bpx and fpx pins. reset clears the lcde bit. 1 = lcd driver module enabled 0 = lcd driver module disabled fc ? fast charge lc ? low current these read/write bits are used to select the value of the resistors in resistor ladder for lcd voltages. reset clears the fc and lc bits. address: $0051 bit 7654321bit 0 read: lcde 0 fc lc lccon3 lccon2 lccon1 lccon0 write: reset:00000000 = unimplemented figure 16-16. lcd control register (lcdcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) technical data mc68HC908LJ12 ? rev. 2.0 336 liquid crystal display driver (lcd) motorola lccon[3:0] ? lcd contrast control these read/write bits select the bias voltage, v bias . this voltage controls the contrast of the lcd. maximum contrast is set when lccon[3:0] = 0000; minimum contrast is when lccon[3:0] = 1111. table 16-2. resistor ladder selection fc lc action x0 each resistor is approximately 37 k ? (default) 01 each resistor is approximately 146 k ? 11 fast charge mode table 16-3. lcd bias voltage control lccon3 lccon2 lccon1 lccon0 bias voltage (% of v dd ) 0000 0.6% 0001 2.9% 0010 5.2% 0011 7.4% 0100 9.6% 0101 11.6% 0110 13.5% 0111 15.3% 1000 17.2% 1001 18.8% 1010 20.5% 1011 22.0% 1100 23.6% 1101 25.0% 1110 26.4% 1111 27.7% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola liquid crystal display driver (lcd) 337 16.9.2 lcd clock register (lcdclk) the lcd clock register (lcdclk): selects the fast charge duty cycle selects lcd driver duty cycle selects lcd waveform base clock fcctl[1:0] ? fast charge duty cycle select these read/write bits select the duty cycle of the fast charge duration. reset clears these bits. (see 16.5.4 fast charge and low current ) address: $004f bit 7654321bit 0 read: 0 fcctl1 fcctl0 duty1 duty0 lclk2 lclk1 lclk0 write: reset:00000000 = unimplemented figure 16-17. lcd clock register (lcdclk) table 16-4. fast charge duty cycle selection fcctl1:fcctl0 fast charge duty cycle 00 in each lcdclk/2 period, each bias resistor is reduced to 37 k ? for a duration of lcdclk/32. 01 in each lcdclk/2 period, each bias resistor is reduced to 37 k ? for a duration of lcdclk/64. 10 in each lcdclk/2 period, each bias resistor is reduced to 37 k ? for a duration of lcdclk/128. 11 not used f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) technical data mc68HC908LJ12 ? rev. 2.0 338 liquid crystal display driver (lcd) motorola duty[1:0] ? duty cycle select these read/write bits select the duty cycle of the lcd driver output waveforms. the multiplexed fp0/bp3 pin is controlled by the duty cycle selected. reset clears these bits. lclk[2:0] ? lcd waveform base clock select these read/write bits selects the lcd waveform base clock. reset clears these bits. table 16-5. lcd duty cycle selection duty1:duty0 description 00 static selected; fp0/bp3 pin function as fp0. 01 1/3 duty cycle selected; fp0/bp3 pin functions as fp0. 10 1/4 duty cycle selected; fp0/bp3 pin functions as bp3. 11 not used table 16-6. lcd waveform base clock selection lclk2 lclk1 lclk0 divide ratio lcd waveform base clock frequency lcdclk (hz) lcd frame rate f xtal (1) = 32.768khz lcd frame rate f xtal = 4.9152mhz f xtal = 32.768khz f xtal = 4.9152mhz 1/3 duty 1/4 duty 1/3 duty 1/4 duty 000128256 ? 85.3 64 ?? 001256128 ? 42.7 32 ?? 01051264 ? 21.3 16 ?? 0 1 1 1024 32 ? 10.7 8 ?? 1 0 0 16384 ? 300 ?? 100 75 1 0 1 32768 ? 150 ?? 50 37.5 1 1 0 65536 ? 75 ?? 25 18.75 111 reserved notes : 1. f xtal is the same as cgmxclk (see section 7. oscillator (osc) ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) i/o registers mc68HC908LJ12 ? rev. 2.0 technical data motorola liquid crystal display driver (lcd) 339 16.9.3 lcd data registers (ldat1 ? ldat14) the fourteen (14) lcd data registers enable and disable the drive to the corresponding lcd segments. addr.register name bit 7654321bit 0 $0052 lcd data register 1 (ldat1) read: f1b3 f1b2 f1b1 f1b0 f0b3 f0b2 f0b1 f0b0 write: reset:uuuuuuuu $0053 lcd data register 2 (ldat2) read: f3b3 f3b2 f3b1 f3b0 f2b3 f2b2 f2b1 f2b0 write: reset:uuuuuuuu $0054 lcd data register 3 (ldat3) read: f5b3 f5b2 f5b1 f5b0 f4b3 f4b2 f4b1 f4b0 write: reset:uuuuuuuu $0055 lcd data register 4 (ldat4) read: f7b3 f7b2 f7b1 f7b0 f6b3 f6b2 f6b1 f6b0 write: reset:uuuuuuuu $0056 lcd data register 5 (ldat5) read: f9b3 f9b2 f9b1 f9b0 f8b3 f8b2 f8b1 f8b0 write: reset:uuuuuuuu $0057 lcd data register 6 (ldat6) read: f11b3 f11b2 f11b1 f11b0 f10b3 f10b2 f10b1 f10b0 write: reset:uuuuuuuu $0058 lcd data register 7 (ldat7) read: f13b3 f13b2 f13b1 f13b0 f12b3 f12b2 f12b1 f12b0 write: reset:uuuuuuuu $0059 lcd data register 8 (ldat8) read: f15b3 f15b2 f15b1 f15b0 f14b3 f14b2 f14b1 f14b0 write: reset:uuuuuuuu $005a lcd data register 9 (ldat9) read: f17b3 f17b2 f17b1 f17b0 f16b3 f16b2 f16b1 f16b0 write: reset:uuuuuuuu u = unaffected = unimplemented figure 16-18. lcd data registers 1 ? 14 (ldat1 ? ldat14) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . liquid crystal display driver (lcd) technical data mc68HC908LJ12 ? rev. 2.0 340 liquid crystal display driver (lcd) motorola $005b lcd data register 10 (ldat10) read: f19b3 f19b2 f19b1 f19b0 f18b3 f18b2 f18b1 f18b0 write: reset:uuuuuuuu $005c lcd data register 11 (ldat11) read: f21b3 f21b2 f21b1 f21b0 f20b3 f20b2 f20b1 f20b0 write: reset:uuuuuuuu $005d lcd data register 12 (ldat12) read: f23b3 f23b2 f23b1 f23b0 f22b3 f22b2 f22b1 f22b0 write: reset:uuuuuuuu $005e lcd data register 13 (ldat13) read: f25b3 f25b2 f25b1 f25b0 f24b3 f24b2 f24b1 f24b0 write: reset:uuuuuuuu $005f lcd data register 14 (ldat14) read: f26b3 f26b2 f26b1 f26b0 write: reset:uuuuuuuu u = unaffected = unimplemented figure 16-18. lcd data registers 1 ? 14 (ldat1 ? ldat14) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola input/output (i/o) ports 341 technical data ? mc68HC908LJ12 section 17. input/output (i/o) ports 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 17.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 17.3.1 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . 344 17.3.2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 345 17.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 17.4.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 347 17.4.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 348 17.4.3 port b led control register (ledb) . . . . . . . . . . . . . . . . . 350 17.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 17.5.1 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . 351 17.5.2 data direction register c (ddrc). . . . . . . . . . . . . . . . . . . 352 17.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 17.6.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 354 17.6.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 355 17.2 introduction thirty-two (32) bidirectional input-output (i/o) pins form four parallel ports. all i/o pins are programmable as inputs or outputs. note: connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68HC908LJ12 ? rev. 2.0 342 input/output (i/o) ports motorola addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $000c port-b led control register (ledb) read: 0 0 ledb5 ledb4 ledb3 ledb2 ledb1 ledb0 write: reset:00000000 figure 17-1. i/o port register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports introduction mc68HC908LJ12 ? rev. 2.0 technical data motorola input/output (i/o) ports 343 table 17-1. port control register bits summary port bit ddr module control pin module register control bit a 0 ddra0 kbi kbier ($001c) kbie0 pta0/kbi0 1 ddra1 kbie1 pta1/kbi1 2 ddra2 kbie2 pta2/kbi2 3 ddra3 kbie3 pta3/kbi3 4 ddra4 adc adscr ($003c) adch[4:0] pta4/atd0 5 ddra5 pta5/atd1 6 ddra6 pta6/atd2 7 ddra7 pta7/atd3 b 0 ddrb0 sci scc1 ($0013) ensci ptb0/txd 1 ddrb1 ptb1/rxd 2 ddrb2 tim1 t1sc0 ($0025) els0b:els0a ptb2/t1ch0 3 ddrb3 t1sc1 ($0028) els1b:els1a ptb3/t1ch1 4 ddrb4 tim2 t2sc0 ($0030) els0b:els0a ptb4/t2ch0 5 ddrb5 t2sc1 ($0033) els1b:els1a ptb5/t2ch1 6 ddrb6 adc adscr ($003c) adch[4:0] ptb6/atd4 7 ddrb7 ptb7/atd5 c 0 ddrc0 lcd config2 ($001d) pcel ptc0/fp19 1 ddrc1 ptc1/fp20 2 ddrc2 ptc2/fp21 3 ddrc3 ptc3/fp22 4 ddrc4 pceh ptc4/fp23 5 ddrc5 ptc5/fp24 6 ddrc6 ptc6/fp25 7 ddrc7 ptc7/fp26 d 0 ddrd0 spi spcr ($0010) spe ptd0/ss 1 ddrd1 ptd1/miso 2 ddrd2 ptd2/mosi 3 ddrd3 ptd3/spsck 4 ddrd4 kbi kbier ($001c) kbie4 ptd4/kbi4 5 ddrd5 kbie5 ptd5/kbi5 6 ddrd6 kbie6 ptd6/kbi6 7 ddrd7 kbie7 ptd7/kbi7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68HC908LJ12 ? rev. 2.0 344 input/output (i/o) ports motorola 17.3 port a port a is an 8-bit special function port that shares four of its port pins with the analog-to-digital converter (adc) module and four of its port pins with the keyboard interrupt module (kbi). 17.3.1 port a data register (pta) the port a data register contains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. kbi[3:0] ? keyboard interrupt channels 0 to 3 kbi[3:0] are input pins to the keyboard interrupt module. the corresponding control bits, kbie[3:0], in the keyboard interrupt enable register, kbier, select which port pins will be used as a keyboard interrupt input and overrides any control from the port i/o logic. see section 19. keyboard interrupt module (kbi) . address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternative function: adc3 adc2 adc1 adc0 kbi3 kbi2 kbi1 kbi0 figure 17-2. port a data register (pta) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port a mc68HC908LJ12 ? rev. 2.0 technical data motorola input/output (i/o) ports 345 adc[3:0] ? adc channels 3 to 0 adc[3:0] are pins used for the input channels to the analog-to-digital converter module. the channel select bits, adch[4:0], in the adc status and control register define which port pin will be used as an adc input and overrides any control from the port i/o logic. see section 15. analog-to-digital converter (adc) . note: care must be taken when reading port a while applying analog voltages to adc[3:0] pins. if the appropriate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptax/adcx pin, while pta is read as a digital input. those ports not selected as analog input channels are considered digital i/o ports. 17.3.2 data direction register a (ddra) data direction register a determines whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables the output buffer for the corresponding port a pin; a logic 0 disables the output buffer. ddra[7:0] ? data direction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 17-4 shows the port a i/o logic. address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 17-3. data direction register a (ddra) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68HC908LJ12 ? rev. 2.0 346 input/output (i/o) ports motorola figure 17-4. port a i/o circuit when ddrax is a logic 1, reading address $0000 reads the ptax data latch. when ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-2 summarizes the operation of the port a pins. table 17-2. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0x (1) notes : 1. x = don ? t care. input, hi-z (2) 2. hi-z = high impedance. ddra[7:0] pin pta[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddra[7:0] pta[7:0] pta[7:0] read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port b mc68HC908LJ12 ? rev. 2.0 technical data motorola input/output (i/o) ports 347 17.4 port b port b is a 8-bit special function port that shares two of its port pins with the infrared serial communication interface (irsci) module, two of its port pins with the timer interface module 1 (tim1) module, two of its port pins with the timer interface module 2 (tim2), and two of its port pins with the adc module. port pins ptb0 ? ptb5 can be configured for direct led drive. 17.4.1 port b data register (ptb) the port b data register contains a data latch for each of the eight port b pins. note: bit 4 ? bit 7 of ptb are not available in a 52-pin lqfp. ptb[7:0] ? port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. txd, rxd ? sci data i/o pins the txd and rxd pins are the transmit data output and receive data input for the irsci module. the enable sci bit, ensci, in the sci control register 1 enables the ptb0/txd and ptb1/rxd pins as sci txd and rxd pins and overrides any control from the port i/o. see section 13. infrared serial communications interface module (irsci) . address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternative function: adc5 adc4 t2ch1 t2ch0 t1ch1 t1ch0 rxd txd additional function: led drive led drive led drive led drive led drive led drive figure 17-5. port b data register (ptb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68HC908LJ12 ? rev. 2.0 348 input/output (i/o) ports motorola t1ch[1:0] ? timer 1 channel i/o bits the t1ch1 and t1ch0 pins are the tim1 input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the ptb2/t1ch0 and ptb3/t1ch1 pins are timer channel i/o pins or general-purpose i/o pins. see section 11. timer interface module (tim) . t2ch[1:0] ? timer 2 channel i/o bits the t2ch1 and t2ch0 pins are the tim1 input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the ptb4/t2ch0 and ptb5/t2ch1 pins are timer channel i/o pins or general-purpose i/o pins. see section 11. timer interface module (tim) . adc[5:4] ? adc channels 5 and 4 adc[5:4] are pins used for the input channels to the analog-to-digital converter module. the channel select bits, adch[4:0], in the adc status and control register define which port pin will be used as an adc input and overrides any control from the port i/o logic. see section 15. analog-to-digital converter (adc) . note: care must be taken when reading port b while applying analog voltages to adc[5:4] pins. if the appropriate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptbx/adcx pin, while ptb is read as a digital input. those ports not selected as analog input channels are considered digital i/o ports. led drive ? direct led drive pins ptb0 ? ptb5 pins can be configured for direct led drive. see 17.4.3 port b led control register (ledb) . 17.4.2 data direction register b (ddrb) data direction register b determines whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables the output buffer for the corresponding port b pin; a logic 0 disables the output buffer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port b mc68HC908LJ12 ? rev. 2.0 technical data motorola input/output (i/o) ports 349 note: for those devices packaged in a 52-pin lqfp, ptb4 ? ptb7 are not connected. ddrb4 ? ddrb7 should be set to a 1 to configure ptb4 ? ptb7 as outputs. ddrb[7:0] ? data direction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pins by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 17-7 shows the port b i/o logic. figure 17-7. port b i/o circuit when ddrbx is a logic 1, reading address $0001 reads the ptbx data latch. when ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 17-6. data direction register b (ddrb) read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68HC908LJ12 ? rev. 2.0 350 input/output (i/o) ports motorola table 17-3 summarizes the operation of the port b pins. 17.4.3 port b led control register (ledb) the port-b led control register (ledb) controls the direct led drive capability on ptb5 ? ptb0 pins. each bit is individually configurable and requires that the data direction register, ddrb, bit be configured as an output. when the irsci is enabled, setting the ledb0 bit also enables high current (15ma) sink capability for the txd pin. ledb[5:0] ? port b led drive enable bits these read/write bits are software programmable to enable the direct led drive on an output port pin. 1 = corresponding port b pin configured for direct led drive: 15ma current sinking capability on ptb[1:0], and 8ma current sinking capability on ptb[5:2] 0 = corresponding port b pin configured for standard drive table 17-3. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) notes : 1. x = don ? t care. input, hi-z (2) 2. hi-z = high impedance. ddrb[7:0] pin ptb[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] address: $000c bit 7654321bit 0 read: 0 0 ledb5 ledb4 ledb3 ledb2 ledb1 ledb0 write: reset:00000000 figure 17-8. port b led control register (ledb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port c mc68HC908LJ12 ? rev. 2.0 technical data motorola input/output (i/o) ports 351 17.5 port c port c is an 8-bit special function port that shares all of its port pins with the liquid crystal display (lcd) driver module. 17.5.1 port c data register (ptc) the port c data register contains a data latch for each of the eight port c pins. ptc[7:0] ? port c data bits these read/write bits are software programmable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. fp[26:19] ? lcd driver frontplanes 26 ? 19 fp[26:19] are pins used for the frontplane output of the lcd driver module. the enable bits, pceh and pcel, in the config2 register, determine whether the ptc7/fp26 ? ptc4/fp23 and ptc3/fp22 ? ptc0/fp19 pins are lcd frontplane driver pins or general-purpose i/o pins. see section 16. liquid crystal display driver (lcd) . address: $0002 bit 7654321bit 0 read: ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset alternative function: fp26 fp25 fp24 fp23 fp22 fp21 fp20 fp19 figure 17-9. port c data register (ptc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68HC908LJ12 ? rev. 2.0 352 input/output (i/o) ports motorola 17.5.2 data direction register c (ddrc) data direction register c determines whether each port c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a logic 0 disables the output buffer. ddrc[7:0] ? data direction register c bits these read/write bits control port c data direction. reset clears ddrc[7:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writing to the port c data register before changing data direction register c bits from 0 to 1. figure 17-11 shows the port c i/o logic. figure 17-11. port c i/o circuit address: $0006 bit 7654321bit 0 read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 figure 17-10. data direction register b (ddrb) read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port c mc68HC908LJ12 ? rev. 2.0 technical data motorola input/output (i/o) ports 353 when ddrcx is a logic 1, reading address $0002 reads the ptcx data latch. when ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-4 summarizes the operation of the port c pins. table 17-4. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0x (1) notes : 1. x = don ? t care; except ptc2. input, hi-z (2) 2. hi-z = high impedance. ddrc[7:0] pin ptc[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrc[7:0] ptc[7:0] ptc[7:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68HC908LJ12 ? rev. 2.0 354 input/output (i/o) ports motorola 17.6 port d port d is an 8-bit special function port that shares four of its pins with serial peripheral interface (spi) module and four of its pins with the keyboard interrupt module (kbi). note: port d is not available in a 52-pin lqfp. 17.6.1 port d data register (ptd) the port d data register contains a data latch for each of the eight port d pins. note: bit 0 ? bit 7 of ptd are not available in a 52-pin lqfp. ptd[7:0] ? port d data bits these read/write bits are software programmable. data direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. ss , miso, mosi, and spsck ? spi functional pins these are the chip select, master-input-slave-output, master-output- slave-input and clock pins for the spi module. the spi enable bit, spe, in the spi control register, spcr, enables these pins as the spi functional pins and overrides any control from port i/o logic. see section 14. serial peripheral interface module (spi) . address: $0003 bit 7654321bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternative function: kbi7 kbi6 kbi5 kbi4 spsck mosi miso ss figure 17-12. port d data register (ptd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port d mc68HC908LJ12 ? rev. 2.0 technical data motorola input/output (i/o) ports 355 kbi[7:4] ? keyboard interrupt pins kbi[7:4] are input pins to the keyboard interrupt module. the corresponding control bits, kbie[7:4], in the keyboard interrupt enable register, kbier, select which port pins will be used as a keyboard interrupt input and overrides any control from the port i/o logic. see section 19. keyboard interrupt module (kbi) 17.6.2 data direction register d (ddrd) data direction register d determines whether each port d pin is an input or an output. writing a logic 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a logic 0 disables the output buffer. note: for those devices packaged in a 52-pin lqfp, ptd0 ? ptd7 are not connected. ddrd0 ? ddrd7 should be set to a 1 to configure ptd0 ? ptd7 as outputs. ddrd[7:0] ? data direction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note: avoid glitches on port d pins by writing to the port d data register before changing data direction register d bits from 0 to 1. figure 17-14 shows the port d i/o logic. address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 17-13. data direction register d (ddrd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68HC908LJ12 ? rev. 2.0 356 input/output (i/o) ports motorola figure 17-14. port d i/o circuit when ddrdx is a logic 1, reading address $0003 reads the ptdx data latch. when ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-5 summarizes the operation of the port d pins. table 17-5. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0x (1) notes : 1. x = don ? t care. input, hi-z (2) 2. hi-z = high impedance. ddrd[7:0] pin ptd[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrd[7:0] ptd[7:0] ptd[7:0] read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola external interrupt (irq) 357 technical data ? mc68HC908LJ12 section 18. external interrupt (irq) 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 18.4.1 irq pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 18.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . .361 18.6 irq status and control register (intscr) . . . . . . . . . . . . . . 361 18.2 introduction the external interrupt (irq) module provides a maskable interrupt input. 18.3 features features of the irq module include the following: a dedicated external interrupt pin (irq ) irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge internal pullup resistor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data mc68HC908LJ12 ? rev. 2.0 358 external interrupt (irq) motorola 18.4 functional description a logic 0 applied to the external interrupt pin can latch a cpu interrupt request. figure 18-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of the following actions occurs: vector fetch ? a vector fetch automatically generates an interrupt acknowledge signal that clears the irq latch. software clear ? software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (intscr). writing a logic 1 to the ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is falling-edge-triggered and is software- configurable to be either falling-edge or low-level-triggered. the mode bit in the intscr controls the triggering sensitivity of the irq pin. when the interrupt pin is edge-triggered only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both falling-edge and low-level-triggered, the cpu interrupt request remains set until both of the following occur: vector fetch or software clear return of the interrupt pin to logic 1 the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask bit in the intscr mask all external interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the imask bit is clear. note: the interrupt mask (i) in the condition code register (ccr) masks all interrupt requests, including external interrupt requests. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola external interrupt (irq) 359 figure 18-1. irq module block diagram imask dq ck clr irq high interrupt to mode select logic request v dd mode voltage detect irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset ack irq synchronizer v dd internal pullup device addr.register name bit 7654321bit 0 $001e irq status and control register (intscr) read: 0000irqf0 imask mode write: ack reset:00000000 = unimplemented table 18-1. irq i/o port register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data mc68HC908LJ12 ? rev. 2.0 360 external interrupt (irq) motorola 18.4.1 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode bit is set, the irq pin is both falling-edge-sensitive and low- level-sensitive. with mode set, both of the following actions must occur to clear irq: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a logic 1 to the ack bit in the interrupt status and control register (intscr). the ack bit is useful in applications that poll the irq pin and require software to clear the irq latch. writing to the ack bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bit latches another interrupt request. if the irq mask bit, imask, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, irq remains active. the vector fetch or software clear and the return of the irq pin to logic 1 may occur in any order. the interrupt request remains pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge-sensitive only. with mode clear, a vector fetch or software clear immediately clears the irq latch. the irqf bit in the intscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it useful in applications where polling is preferred. use the bih of bil instruction to read the logic level on the irq pin. note: when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) irq module during break interrupts mc68HC908LJ12 ? rev. 2.0 technical data motorola external interrupt (irq) 361 18.5 irq module during break interrupts the system integration module (sim) controls whether the irq latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear the latches during the break state. (see section 22. break module (brk) .) to allow software to clear the irq latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latches during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq latch. 18.6 irq status and control register (intscr) the irq status and control register (intscr) controls and monitors operation of the irq module. the intscr has the following functions: shows the state of the irq flag clears the irq latch masks irq and interrupt request controls triggering sensitivity of the irq interrupt pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data mc68HC908LJ12 ? rev. 2.0 362 external interrupt (irq) motorola irqf ? irq flag bit this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack always reads as logic 0. reset clears ack. imask ? irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only address: $001e bit 7654321bit 0 read: 0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 18-2. irq status and control register (intscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola keyboard interrupt module (kbi) 363 technical data ? mc68HC908LJ12 section 19. keyboard interrupt module (kbi) 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 19.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 19.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 19.5.1 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 19.6 keyboard interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . 367 19.6.1 keyboard status and control register. . . . . . . . . . . . . . . . 368 19.6.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 369 19.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 19.8 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 19.9 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370 19.10 keyboard module during break interrupts . . . . . . . . . . . . . . .370 19.2 introduction the keyboard interrupt module (kbi) provides eight independently maskable external interrupts which are accessible via pta0 ? pta3 and ptd4 ? ptd7. when a port pin is enabled for keyboard interrupt function, an internal 30k ? pullup device is also enabled on the pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data mc68HC908LJ12 ? rev. 2.0 364 keyboard interrupt module (kbi) motorola 19.3 features features of the keyboard interrupt module include the following: eight keyboard interrupt pins with pullup devices separate keyboard interrupt enable bits and one keyboard interrupt mask programmable edge-only or edge- and level- interrupt sensitivity exit from low-lower modes 19.4 i/o pins the eight keyboard interrupt pins are shared with standard port i/o pins. the full name of the kbi pins are listed in table 19-1 . the generic pin name appear in the text that follows. addr.register name bit 7654321bit 0 $001b keyboard status and control register (kbscr) read: 0000keyf0 imaskk modek write: ackk reset:00000000 $001c keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 19-1. kbi i/o register summary table 19-1. pin name conventions kbi generic pin name full mcu pin name pin selected for kbi function by kbiex bit in kbier kbi0 ? kbi3 pta0/kbi0 ? pta3/kbi3 kbie0 ? kbie3 kbi4 ? kbi7 ptd4/kbi4 ? ptd7/kbi7 kbie4 ? kbie7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola keyboard interrupt module (kbi) 365 19.5 functional description figure 19-2. keyboard interrupt block diagram writing to the kbie7 ? kbie0 bits in the keyboard interrupt enable register independently enables or disables a port a or port d pin as a keyboard interrupt pin. enabling a keyboard interrupt pin in port a or port d also enables its internal pull-up device. a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. if the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: kbie0 kbie7 . . . dq ck clr v dd modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kbi7 kbi0 synchronizer keyf to pullup enable to pullup enable keyboard interrupt request f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data mc68HC908LJ12 ? rev. 2.0 366 keyboard interrupt module (kbi) motorola vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the interrupt acknowledge signal by writing a logic 1 to the ackk bit in the keyboard status and control register kbscr. the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $ffdf and $ffde. return of all enabled keyboard interrupt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the keyboard interrupt pin is falling-edge- sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note: setting a keyboard interrupt enable bit (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a logic 0 for software to read the pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) keyboard interrupt registers mc68HC908LJ12 ? rev. 2.0 technical data motorola keyboard interrupt module (kbi) 367 19.5.1 keyboard initialization when a keyboard interrupt pin is enabled, it takes time for the internal pull-up to reach a logic 1. therefore a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. an interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddr bits in data direction register. 2. write logic 1s to the appropriate data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 19.6 keyboard interrupt registers two registers control the operation of the keyboard interrupt module: keyboard status and control register keyboard interrupt enable register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data mc68HC908LJ12 ? rev. 2.0 368 keyboard interrupt module (kbi) motorola 19.6.1 keyboard status and control register flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity keyf ? keyboard flag bit this read-only bit is set when a keyboard interrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a logic 1 to this write-only bit clears the keyboard interrupt request. ackk always reads as logic 0. reset clears ackk. imaskk ? keyboard interrupt mask bit writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only address: $001b bit 7654321bit 0 read: 0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 19-3. keyboard status and control register (kbscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) low-power modes mc68HC908LJ12 ? rev. 2.0 technical data motorola keyboard interrupt module (kbi) 369 19.6.2 keyboard interrupt enable register the keyboard interrupt enable register individually enables or disables the pta0/kbi0 ? pta3/kbi3 and ptd4/kbi4 ? ptd7/kbi7 pins to operate as a keyboard interrupt pin. kbie7 ? kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = kbix pin enabled as keyboard interrupt pin 0 = kbix pin not enabled as keyboard interrupt pin 19.7 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 19.8 wait mode the keyboard interrupt module remains active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. address: $001c bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 19-4. keyboard interrupt enable register (kbier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data mc68HC908LJ12 ? rev. 2.0 370 keyboard interrupt module (kbi) motorola 19.9 stop mode the keyboard interrupt module remains active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 19.10 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during the break state. the bcfe bit in the sim break flag control register (bfcr) enables software to clear status bits during the break state. to allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break state has no effect. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola computer operating properly (cop) 371 technical data ? mc68HC908LJ12 section 20. computer operating properly (cop) 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 20.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 20.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 20.4.1 iclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 20.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 20.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 20.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 20.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 20.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 20.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 20.4.8 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . 374 20.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 20.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 20.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 20.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375 20.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 20.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376 20.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . .376 20.2 introduction the computer operating properly (cop) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in the configuration register 1 (config1). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data mc68HC908LJ12 ? rev. 2.0 372 computer operating properly (cop) motorola 20.3 functional description figure 20-1 shows the structure of the cop module. figure 20-1. cop block diagram the cop counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ? 2 4 or 2 13 ? 2 4 iclk cycles, depending on the state of the cop rate select bit, coprs, in the config1 register. with a 2 13 ? 2 4 iclk cycle overflow option, a 47-khz iclk gives a cop timeout period of 174ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12 through 5 of the prescaler. note: service the cop immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. copctl write iclk reset vector fetch reset circuit reset status register internal reset sources 12-bit cop prescaler clear all stages 6-bit cop counter cop disable reset copctl write clear copen (from sim) cop counter cop clock cop timeout stop instruction (copd from config1) cop rate sel (coprs from config1) clear stages 5 ? 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) i/o signals mc68HC908LJ12 ? rev. 2.0 technical data motorola computer operating properly (cop) 373 a cop reset pulls the rst pin low for 32 iclk cycles and sets the cop bit in the sim reset status register (srsr). in monitor mode, the cop is disabled if the rst pin or the irq1 is held at v tst . during the break state, v tst on the rst pin disables the cop. note: place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt subroutine could keep the cop from generating a reset even while the main program is not working properly. 20.4 i/o signals the following paragraphs describe the signals shown in figure 20-1 . 20.4.1 iclk iclk is the internal oscillator output signal. iclk frequency is approximately equal to 47-khz. see section 23. electrical specifications for iclk parameters. 20.4.2 stop instruction the stop instruction clears the cop prescaler. 20.4.3 copctl write writing any value to the cop control register (copctl) (see 20.5 cop control register ) clears the cop counter and clears bits 12 through 5 of the prescaler. reading the cop control register returns the low byte of the reset vector. 20.4.4 power-on reset the power-on reset (por) circuit clears the cop prescaler 4096 iclk cycles after power-up. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data mc68HC908LJ12 ? rev. 2.0 374 computer operating properly (cop) motorola 20.4.5 internal reset an internal reset clears the cop prescaler and the cop counter. 20.4.6 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the cop prescaler. 20.4.7 copd (cop disable) the copd signal reflects the state of the cop disable bit (copd) in the config1 register. (see figure 20-2 and section 5. configuration registers (config) .) 20.4.8 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the config1 register. coprs ? cop rate select coprs selects the cop time-out period. reset clears coprs. 1 = cop time out period = 2 13 ? 2 4 iclk cycles 0 = cop time out period = 2 18 ? 2 4 iclk cycles copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: coprs lvistop lvirstd lvipwrd 0 ssrec stop copd write: reset:00010000 = unimplemented figure 20-2. configuration register 1 (config1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) cop control register mc68HC908LJ12 ? rev. 2.0 technical data motorola computer operating properly (cop) 375 20.5 cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 20.6 interrupts the cop does not generate cpu interrupt requests. 20.7 monitor mode when monitor mode is entered with v tst on the irq pin, the cop is disabled as long as v tst remains on the irq pin or the rst pin. when monitor mode is entered by having blank reset vectors and not having v tst on the irq pin, the cop is automatically disabled until a por occurs. 20.8 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 20-3. cop control register (copctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data mc68HC908LJ12 ? rev. 2.0 376 computer operating properly (cop) motorola 20.8.1 wait mode the cop remains active during wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. 20.8.2 stop mode stop mode turns off the iclk input to the cop and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. to prevent inadvertently turning off the cop with a stop instruction, a configuration option is available that disables the stop instruction. when the stop bit in the configuration register has the stop instruction is disabled, execution of a stop instruction results in an illegal opcode reset. 20.9 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola low-voltage inhibit (lvi) 377 technical data ? mc68HC908LJ12 section 21. low-voltage inhibit (lvi) 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 21.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 21.4.1 interrupt lvi operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 21.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 21.4.3 voltage hysteresis protection . . . . . . . . . . . . . . . . . . . . . . 380 21.4.4 lvi trip selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 21.5 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 21.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 21.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 21.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 21.2 introduction this section describes the low-voltage inhibit (lvi) module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls below the lvi trip falling voltage, v tripf . 21.3 features features of the lvi module include: programmable lvi interrupt and reset selectable lvi trip voltage programmable stop mode operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) technical data mc68HC908LJ12 ? rev. 2.0 378 low-voltage inhibit (lvi) motorola 21.4 functional description figure 21-2 shows the structure of the lvi module. figure 21-2. lvi module block diagram the lvi is disabled out of reset. the lvi module contains a bandgap reference circuit and comparator. clearing the lvi power disable bit, lvipwrd, enables the lvi to monitor v dd voltage. clearing the lvi reset disable bit, lvirstd, enables the lvi module to generate a reset when v dd falls below a voltage, v tripf . setting the lvi enable in stop mode bit, lvistop, enables the lvi to operate in stop mode. addr.register name bit 7654321bit 0 $fe0f low-voltage inhibit status register (lvisr) read: lviout lviie lviif00000 write: lviiak reset:00000000 = unimplemented figure 21-1. lvi i/o register summary low v dd detector lvipwrd stop instruction lvi reset v dd > v tripr = 0 v dd v tripf = 1 from config1 from config1 v dd from config1 lvisel[1:0] from config2 to lvisr lvistop lvirstd interrupt request lvi lviout to lvisr edge detect latch clr from lvisr lviie lviif from lvisr lviiack default disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola low-voltage inhibit (lvi) 379 the lvi trip point selection bits, lvisel[1:0], select the trip point voltage, v tripf , to be configured for 5v or 3.3v operation. the actual trip points are shown in section 23. electrical specifications . setting lvi interrupt enable bit, lviie, enables lvi interrupts whenever the lviout bit toggles (from logic 0 to logic 1, or from logic 1 to logic 0). note: after a power-on reset (por) the user must configure the lvisel[1:0} bits for 3.3v or 5v operation before enabling the lvi module (by clearing the lvipwrd bit in config1 register). note: if the user requires 3.3v mode and enables the lvi module after configuring the lvisel[1;0] bits to 3.3v operation mode while the v dd supply is not above the v tripf for 3.3v mode, the mcu will immediately go into reset. the lvi in this case will hold the mcu in reset until either v dd goes above the rising 3.3v trip point, v tripr , which will release reset or v dd decreases to approximately 0v which will re-trigger the power-on reset. lvistop, lvipwrd, lvirstd, and lvisel[1:0] are in the configuration registers. see section 5. configuration registers (config) for details of the lvi ? s configuration bits. once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, v tripr , which causes the mcu to exit reset. see 9.4.2.5 low-voltage inhibit (lvi) reset for details of the interaction between the sim and the lvi. the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr). the lviie, lviif, and lviiak bits in the lvisr control lvi interrupt functions. an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) technical data mc68HC908LJ12 ? rev. 2.0 380 low-voltage inhibit (lvi) motorola 21.4.1 interrupt lvi operation in applications that can operate at v dd levels below the v tripf level, software can monitor v dd by polling the lviout bit, or by setting the lvi interrupt enable bit, lviie, to enable interrupt requests. in the configuration register 1 (config1), the lvipwrd bit must be at logic 0 to enable the lvi module, and the lvirstd bit must be at logic 1 to disable lvi resets. the lvi interrupt flag, lviif, is set whenever the lviout bit changes state (toggles). when lvif is set, a cpu interrupt request is generated if the lviie is also set. in the lvi interrupt service subroutine, lviif bit can be cleared by writing a logic 1 to the lvi interrupt acknowledge bit, lviiak. 21.4.2 forced reset operation in applications that require v dd to remain above the v tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls below the v tripf level. in the configuration register 1 (config1), the lvipwrd and lvirstd bits must be at logic 0 to enable the lvi module and to enable lvi resets. if lviie is set to enable lvi interrupts when lvirstd is cleared, lvi reset has a higher priority over lvi interrupt. in this case, when v dd falls below the v tripf level, an lvi reset will occur, and the lviie bit will be cleared. 21.4.3 voltage hysteresis protection once the lvi has triggered (by having v dd fall below v tripf ), the lvi will maintain a reset condition until v dd rises above the rising trip point voltage, v tripr . this prevents a condition in which the mcu is continually entering and exiting reset if v dd is approximately equal to v tripf . v tripr is greater than v tripf by the hysteresis voltage, v hys . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) lvi status register mc68HC908LJ12 ? rev. 2.0 technical data motorola low-voltage inhibit (lvi) 381 21.4.4 lvi trip selection the trip point selection bits, lvisel[1:0], in the config2 register select whether the lvi is configured for 5v or 3.3 v operation. (see section 5. configuration registers (config) .) note: the mcu is guaranteed to operate at a minimum supply voltage. the trip point (v tripf [5 v] or v tripf [3.3 v]) may be lower than this. (see section 23. electrical specifications for the actual trip point voltages.) 21.5 lvi status register the lvi status register (lvisr) controls lvi interrupt functions and indicates if the v dd voltage was detected below the v tripf level. lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the v tripf trip voltage (see table 21-2 ). reset clears the lviout bit. address: $fe0f bit 7654321bit 0 read: lviout lviie lviif00000 write: lviiak reset:00000000 = unimplemented table 21-1. lvi status register (lvisr) table 21-2. lviout bit indication v dd lviout v dd > v tripr 0 v dd < v tripf 1 v tripf < v dd < v tripr previous value f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) technical data mc68HC908LJ12 ? rev. 2.0 382 low-voltage inhibit (lvi) motorola lviie ? lvi interrupt enable bit this read/write bit enables the lviif bit to generate cpu interrupt requests. reset clears the lviie bit. 1 = lviif can generate cpu interrupt requests 0 = lviif cannot generate cpu interrupt requests lviif ? lvi interrupt flag this clearable, read-only flag is set whenever the lviout bit toggles. reset clears the lviif bit. 1 = lviout has toggled 0 = lviout has not toggled lviiak ? lvi interrupt acknowledge bit writing a logic 1 to this write-only bit clears the lvi interrupt flag, lviif. lviiak always reads as logic 0. 1 = clears lviif bit 0 = no effect 21.6 low-power modes the stop and wait instructions put the mcu in low power- consumption standby modes. 21.6.1 wait mode if enabled, the lvi module remains active in wait mode. if enabled to generate resets or interrupts, the lvi module can generate a reset or an interrupt and bring the mcu out of wait mode. 21.6.2 stop mode if enabled in stop mode (lvistop = 1), the lvi module remains active in stop mode. if enabled to generate resets or interrupts, the lvi module can generate a reset or an interrupt and bring the mcu out of stop mode. note: if enabled to generate both resets and interrupts, there will be no lvi interrupts, as resets have a higher priority. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola break module (brk) 383 technical data ? mc68HC908LJ12 section 22. break module (brk) 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 22.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 22.4.1 flag protection during break interrupts . . . . . . . . . . . . . . .386 22.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 386 22.4.3 tim1 and tim2 during break interrupts. . . . . . . . . . . . . . .386 22.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 386 22.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386 22.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 22.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 22.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 22.6.1 break status and control register. . . . . . . . . . . . . . . . . . .387 22.6.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . .388 22.6.3 sim break status register . . . . . . . . . . . . . . . . . . . . . . . . . 388 22.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . .390 22.2 introduction this section describes the break module. the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) technical data mc68HC908LJ12 ? rev. 2.0 384 break module (brk) motorola 22.3 features features of the break module include: accessible input/output (i/o) registers during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 22.4 functional description when the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the cpu. the cpu then loads the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the address in the program counter) matches the contents of the break address registers. software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated address matches the contents of the break address registers, the break interrupt begins after the cpu completes its current instruction. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 22-1 shows the structure of the break module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) functional description mc68HC908LJ12 ? rev. 2.0 technical data motorola break module (brk) 385 figure 22-1. break module block diagram iab15 ? iab8 iab7 ? iab0 8-bit comparator 8-bit comparator control break address register low break address register high iab15 ? iab0 break addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 22-2. break module i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) technical data mc68HC908LJ12 ? rev. 2.0 386 break module (brk) motorola 22.4.1 flag protection during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. 22.4.2 cpu during break interrupts the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 22.4.3 tim1 and tim2 during break interrupts a break interrupt stops the timer counters. 22.4.4 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 22.5 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 22.5.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the return address on the stack if sbsw is set (see section 9. system integration module (sim) ). clear the sbsw bit by writing logic 0 to it. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) break module registers mc68HC908LJ12 ? rev. 2.0 technical data motorola break module (brk) 387 22.5.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. 22.6 break module registers these registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) sim break status register (sbsr) sim break flag control register (sbfcr) 22.6.1 break status and control register the break status and control register (brkscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled on 16-bit address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 22-3. break status and control register (brkscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) technical data mc68HC908LJ12 ? rev. 2.0 388 break module (brk) motorola brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. reset clears the brka bit. 1 = (when read) break address match 0 = (when read) no break address match 22.6.2 break address registers the break address registers (brkh and brkl) contain the high and low bytes of the desired breakpoint address. reset clears the break address registers. 22.6.3 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. the flag is useful in applications requiring a return to wait mode after exiting from a break interrupt. address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 22-4. break address register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 22-5. break address register low (brkl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) break module registers mc68HC908LJ12 ? rev. 2.0 technical data motorola break module (brk) 389 sbsw ? break wait bit this status bit is set when a break interrupt causes an exit from wait mode or stop mode. clear sbsw by writing a logic 0 to it. reset clears sbsw. 1 = stop mode or wait mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break interrupt routine. the user can modify the return address on the stack by subtracting 1 from it. the following code is an example. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. r= reserved figure 22-6. sim break status register (sbsr) ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) technical data mc68HC908LJ12 ? rev. 2.0 390 break module (brk) motorola 22.6.4 sim break flag control register the sim break flag control register (sbfcr) contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 22-7. sim break flag control register (sbfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola electrical specifications 391 technical data ? mc68HC908LJ12 section 23. electrical specifications 23.1 contents 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 23.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .392 23.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 393 23.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 23.6 5.0v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 394 23.7 3.3v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 396 23.8 5.0v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 23.9 3.3v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 23.10 5.0v oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . 398 23.11 3.3v oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . 398 23.12 5.0v adc electrical characteristics . . . . . . . . . . . . . . . . . . . . 399 23.13 3.3v adc electrical characteristics . . . . . . . . . . . . . . . . . . . . 400 23.14 timer interface module characteristics . . . . . . . . . . . . . . . . . 401 23.15 cgm electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . 401 23.16 5.0v spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 23.17 3.3v spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 23.18 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 406 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68HC908LJ12 ? rev. 2.0 392 electrical specifications motorola 23.2 introduction this section contains electrical and timing specifications. 23.3 absolute maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. note: this device is not guaranteed to operate properly at the maximum ratings. refer to 23.6 5.0v dc electrical characteristics for guaranteed operating conditions. note: this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss ? ?????? ?????????? ? ? ??? : 1. voltages referenced to v ss . characteristic symbol value unit supply voltage v dd ? 0.3 to +6.0 v input voltage all pins (except irq ) irq pin v in v ss ? 0.3 to v dd +0.3 v ss ? 0.3 to 8.5 v maximum current per pin excluding v dd and v ss i 25 ma maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma storage temperature t stg ? 55 to +150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications functional operating range mc68HC908LJ12 ? rev. 2.0 technical data motorola electrical specifications 393 23.4 functional operating range 23.5 thermal characteristics table 23-2. operating range characteristic symbol value unit operating temperature range t a ? 40 to +85 c operating voltage range v dd 3.3v 10% 5.0v 10% v table 23-3. thermal characteristics characteristic symbol value unit thermal resistance 52-pin lqfp 64-pin lqfp 64-pin qfp ja 85 80 70 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) notes : 1. power dissipation is a function of temperature. p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c) + p d 2 ja w/ c average junction temperature t j t a + (p d ja ) c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68HC908LJ12 ? rev. 2.0 394 electrical specifications motorola 23.6 5.0v dc electrical characteristics table 23-4. 5.0v dc electrical characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ? 2.0 ma) all ports v oh v dd ? 0.8 ?? v output low voltage (i load = 1.6ma) all ports (i load = 8.0 ma) ptb2 ? ptb5 (i load = 15.0 ma) ptb0/txd ? ptb1 v ol ?? 0.4 v input high voltage all ports, rst , irq , osc1 v ih 0.7 v dd ? v dd v input low voltage all ports, rst , irq , osc1 v il v ss ? 0.3 v dd v v dd supply current run (3) , f op = 8 mhz with all modules on with adc on with adc off wait (4) , f op = 8 mhz (all modules off) stop, f op = 8 khz (5) 25 c (with osc, rtc, lcd (6) , lvi on) 25 c (with osc, rtc, lcd (6) on) 25 c (with osc, rtc on) 25 c (all modules off) i dd ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 18 15 12 10 350 50 30 1 ma ma ma ma a a a a digital i/o ports hi-z leakage current all ports, rst i il ?? 10 a input current irq i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (7) v por 0 ? 100 mv por rise-time ramp rate (8) r por 0.035 ?? v/ms monitor mode entry voltage (at irq pin) v tst 1.5 v dd ? 8v pullup resistors (9) pta0 ? pta3, ptd4 ? ptd7 configured as kbi0 ? kbi7 rst , irq r pu1 r pu2 ? ? 28 28 ? ? k ? k ? low-voltage inhibit, trip falling voltage v tripf 4.00 4.32 4.70 v low-voltage inhibit, trip rising voltage v tripr 4.00 4.32 4.70 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 5.0v dc electrical characteristics mc68HC908LJ12 ? rev. 2.0 technical data motorola electrical specifications 395 notes : 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measurements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . 4. wait i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . 5. the 8khz clock is from a 32khz clock input at osc1, for the driving the rtc. 6. lcd driver configured for high current mode. 7. maximum is highest voltage that por is guaranteed. 8. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 9. r pu1 and r pu2 are measured at v dd = 5.0v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68HC908LJ12 ? rev. 2.0 396 electrical specifications motorola 23.7 3.3v dc electrical characteristics table 23-5. 3.3v dc electrical characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ? 1.0 ma) all ports v oh v dd ? 0.4 ?? v output low voltage (i load = 0.8ma) all ports (i load = 4.0 ma) ptb2 ? ptb5 (i load = 10.0 ma) ptb0/txd ? ptb1 v ol ?? 0.4 v input high voltage all ports, rst , irq , osc1 v ih 0.7 v dd ? v dd v input low voltage all ports, rst , irq , osc1 v il v ss ? 0.3 v dd v v dd supply current run (3) , f op = 4 mhz with all modules on with adc on with adc off wait (4) , f op = 4 mhz (all modules off) stop, f op = 8 khz (5) 25 c (with osc, rtc, lcd (6) , lvi on) 25 c (with osc, rtc, lcd (6) on) 25 c (with osc, rtc on) 25 c (all modules off) i dd ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8 6 5 3.5 280 38 25 1 ma ma ma ma a a a a digital i/o ports hi-z leakage current all ports, rst i il ?? 10 a input current irq i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (7) v por 0 ? 100 mv por rise-time ramp rate (8) r por 0.02 ?? v/ms monitor mode entry voltage (at irq pin) v hi 1.5 v dd ? 2 v dd v pullup resistors (9) pta0 ? pta3, ptd4 ? ptd7 configured as kbi0 ? kbi7 rst , irq r pu1 r pu2 ? ? 26 28 ? ? k ? k ? low-voltage inhibit, trip falling voltage v tripf 2.40 2.57 2.88 v low-voltage inhibit, trip rising voltage v tripr 2.46 2.63 2.97 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 5.0v control timing mc68HC908LJ12 ? rev. 2.0 technical data motorola electrical specifications 397 23.8 5.0v control timing 23.9 3.3v control timing notes : 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measurements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . 4. wait i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . 5. the 8khz clock is from a 32khz clock input at osc1, for the driving the rtc. 6. lcd driver configured for high current mode. 7. maximum is highest voltage that por is guaranteed. 8. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 9. r pu1 and r pu2 are measured at v dd = 3.3v. table 23-6. 5.0v control timing characteristic (1) notes : 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. f op ? 8mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 750 ? ns table 23-7. 3.3v control timing characteristic (1) notes : 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. f op ? 4mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 1.5 ? s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68HC908LJ12 ? rev. 2.0 398 electrical specifications motorola 23.10 5.0v oscillator characteristics 23.11 3.3v oscillator characteristics table 23-8. 5.0v oscillator specifications characteristic symbol min typ max unit internal oscillator clock frequency f iclk 46k 47k (1) notes : 1. typical value reflect average measurements at midpoint of voltage range, 25 c only. 48k hz external reference clock to osc1 (2) 2. no more than 10% duty cycle deviation from 50%. f osc dc ? 20m hz crystal reference frequency (3) 3. fundamental mode crystals only. f xclk 32.768k 4.9152m hz crystal load capacitance (4) 4. consult crystal manufacturer ? s data. c l ??? crystal fixed capacitance c 1 ? 2 c l (25p) ? f crystal tuning capacitance c 2 ? 2 c l (25p) ? f feedback bias resistor r b ? 10m ? ? series resistor (5) 5. not required for high frequency crystals. r s ? 100k ? ? ??? internal oscillator clock frequency f iclk 42.8k 43.4k (1) notes : 1. typical value reflect average measurements at midpoint of voltage range, 25 c only. 44k hz external reference clock to osc1 (2) 2. no more than 10% duty cycle deviation from 50%. f osc dc ? 16m hz crystal reference frequency (3) 3. fundamental mode crystals only. f xclk 32.768k 4.9152m hz crystal load capacitance (4) 4. consult crystal manufacturer ? s data. c l ??? crystal fixed capacitance c 1 ? 2 c l (25p) ? f crystal tuning capacitance c 2 ? 2 c l (25p) ? f feedback bias resistor r b ? 10m ? ? series resistor (5) 5. not required for high frequency crystals. r s ? 100k ? ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 5.0v adc electrical characteristics mc68HC908LJ12 ? rev. 2.0 technical data motorola electrical specifications 399 23.12 5.0v adc electrical characteristics table 23-10. adc 5.0v electrical characteristics characteristic symbol min max unit notes supply voltage v dda 4.5 5.5 v v dda is an dedicated pin and should be tied to v dd on the pcb with proper decoupling. input range v adin 0 v dda v v adin v dda resolution b ad 10 10 bits absolute accuracy a ad ? 1.5 lsb includes quantization. 0.5 lsb = 1 adc count. adc internal clock f adic 32 k 2 m hz t adic = 1/f adic conversion range r ad v refl v refh v adc voltage reference high v refh ? v dda + 0.1 v adc voltage reference low v refl v ssa ? 0.1 ? v v ssa is tied to v ss internally. conversion time t adc 16 17 t adic cycles sample time t ads 5 ? t adic cycles monotonically m ad guaranteed zero input reading z adi 000 001 hex v adin = v refl full-scale reading f adi 3fc 3ff hex v adin = v refh input capacitance c adi ? 20 pf not tested. input impedance r adi 20m ? ? v refh /v refl i vref ? 1.6 ma not tested. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68HC908LJ12 ? rev. 2.0 400 electrical specifications motorola 23.13 3.3v adc electrical characteristics table 23-11. adc 3.3v electrical characteristics characteristic symbol min max unit notes supply voltage v dda 3.0 3.6 v v dda is an dedicated pin and should be tied to v dd on the pcb with proper decoupling. input range v adin 0 v dda v v adin v dda resolution b ad 10 10 bits absolute accuracy a ad ? 1.5 lsb includes quantization. 0.5 lsb = 1 adc count. adc internal clock f adic 32 k 2 m hz t adic = 1/f adic conversion range r ad v refl v refh v adc voltage reference high v refh ? v dda + 0.1 v adc voltage reference low v refl v ssa ? 0.1 ? v v ssa is tied to v ss internally. conversion time t adc 16 17 t adic cycles sample time t ads 5 ? t adic cycles monotonically m ad guaranteed zero input reading z adi 000 001 hex v adin = v refl full-scale reading f adi 3fc 3ff hex v adin = v refh input capacitance c adi ? 20 pf not tested. input impedance r adi 20m ? ? measured at 5v v refh /v refl i vref ? 1.6 ma not tested. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications timer interface module characteristics mc68HC908LJ12 ? rev. 2.0 technical data motorola electrical specifications 401 23.14 timer interface module characteristics 23.15 cgm electrical specifications characteristic symbol min max unit input capture pulse width t tih , t til 1 ? t cyc characteristic symbol min typ max unit reference frequency f rdv 30 32.768 100 khz range nominal multiplies f nom ? 38.4 ? khz vco center-of-range frequency f vrs 38.4k ? 40.0m hz vco range linear range multiplier l 1 ? 255 vco power-of-two-range multiplier 2 e 1 ? 4 vco multiply factor n 1 ? 4095 vco prescale multiplier 2 p 1 ? 8 reference divider factor r 1 1 15 vco operating frequency f vclk 38.4k ? 40.0m hz manual acquisition time t lock ?? 50 ms automatic lock time t lock ?? 50 ms pll jitter (1) notes : 1. deviation of average bus frequency over 2ms. n = vco multiplier. f j 0 ? f rclk 0.025% 2 p n/4 hz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68HC908LJ12 ? rev. 2.0 402 electrical specifications motorola 23.16 5.0v spi characteristics diagram number (1) notes : 1. numbers refer to dimensions in figure 23-1 and figure 23-2 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc t cyc 2 enable lead time t lead(s) 1 ? t cyc 3 enable lag time t lag(s) 1 ? t cyc 4 clock (spsck) high time master slave t sckh(m) t sckh(s) t cyc ? 25 1/2 t cyc ? 25 64 t cyc ? ns ns 5 clock (spsck) low time master slave t sckl(m) t sckl(s) t cyc ? 25 1/2 t cyc ? 25 64 t cyc ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 30 30 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 30 30 ? ? ns ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 40 40 ns ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ? 40 ns 10 data valid time, after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) ? ? 50 50 ns ns 11 data hold time, outputs, after enable edge master slave t ho(m) t ho(s) 0 0 ? ? ns ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3.3v spi characteristics mc68HC908LJ12 ? rev. 2.0 technical data motorola electrical specifications 403 23.17 3.3v spi characteristics diagram number (1) notes : 1. numbers refer to dimensions in figure 23-1 and figure 23-2 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc t cyc 2 enable lead time t lead(s) 1 ? t cyc 3 enable lag time t lag(s) 1 ? t cyc 4 clock (spsck) high time master slave t sckh(m) t sckh(s) t cyc ? 35 1/2 t cyc ? 35 64 t cyc ? ns ns 5 clock (spsck) low time master slave t sckl(m) t sckl(s) t cyc ? 35 1/2 t cyc ? 35 64 t cyc ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 40 40 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 40 40 ? ? ns ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 50 50 ns ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ? 50 ns 10 data valid time, after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) ? ? 60 60 ns ns 11 data hold time, outputs, after enable edge master slave t ho(m) t ho(s) 0 0 ? ? ns ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68HC908LJ12 ? rev. 2.0 404 electrical specifications motorola figure 23-1. spi master timing note note: this first clock edge is generated internally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6 ? 1 lsb in master msb out bits 6 ? 1 master lsb out 11 10 11 7 6 note note: this last clock edge is generated internally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6 ? 1 lsb in master msb out bits 6 ? 1 master lsb out 10 11 10 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) cpol = 0 cpol = 1 cpol = 0 cpol = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3.3v spi characteristics mc68HC908LJ12 ? rev. 2.0 technical data motorola electrical specifications 405 figure 23-2. spi slave timing note: not defined but normally msb of character just received slave ss input spsck input spsck input miso input mosi output 4 5 5 1 4 msb in bits 6 ? 1 8 6 10 5 11 note slave lsb out 9 3 lsb in 2 7 bits 6 ? 1 msb out note: not defined but normally lsb of character previously transmitted slave ss input spsck input spsck input miso output mosi input 4 5 5 1 4 msb in bits 6 ? 1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6 ? 1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 cpol = 0 cpol = 1 cpol = 0 cpol = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68HC908LJ12 ? rev. 2.0 406 electrical specifications motorola 23.18 flash memory characteristics table 23-12. flash memory electrical characteristics characteristic symbol min. max. unit data retention voltage v rdr 1.3 ? v number of rows per page 2 rows number of bytes per page 128 bytes read bus clock frequency f read (1) notes : 1. f read is defined as the frequency range for which the flash memory can be read. 32k 8m hz page erase time t erase (2) 2. if the page erase time is longer than t erase (min.), there is no erase-disturb, but it reduces the endurance of the flash memory. 1 ? ms mass erase time t merase (3) 3. if the mass erase time is longer than t merase (min.), there is no erase-disturb, but is reduces the endurance of the flash memory. 4 ? ms pgm/erase to hven setup time t nvs 10 ? s high-voltage hold time t nvh 5 ? s high-voltage hold time (mass erase) t nvhl 100 ? s program hold time t pgs 5 ? s program time t prog 30 40 s address/data setup time t ads ? 30 ns address/data hold time t adh ? 30 ns recovery time t rcv (4) 4. it is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to logic 0. 1 ? s cumulative hv period t hv (5) 5. t hv is the cumulative high voltage programming time to the same row before next erase, and the same address can not be programmed twice before next erase. ? 25 ms row erase endurance (6) 6. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase/program cycles. ? 10k ? cycles row program endurance (7) 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase/program cycle. ? 10k ? cycles data retention time (8) 8. the flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. ? 10 ? years f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola mechanical specifications 407 technical data ? mc68HC908LJ12 section 24. mechanical specifications 24.1 contents 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 24.3 52-pin low-profile quad flat pack (lqfp) . . . . . . . . . . . . . . 408 24.4 64-pin low-profile quad flat pack (lqfp) . . . . . . . . . . . . . . 409 24.5 64-pin quad flat pack (qfp). . . . . . . . . . . . . . . . . . . . . . . . . 410 24.2 introduction this section gives the dimensions for: 52-pin low-profile quad flat pack (case no. 848d) 64-pin low-profile quad flat pack (case no. 840f) 64-pin quad flat pack (case no. 840b) the following figures show the latest package drawings at the time of this publication. to make sure that you have the latest package specifications, contact one of the following: local motorola sales office world wide web at http://www.motorola.com/semiconductors/ follow the world wide web on-line instructions to retrieve the current mechanical specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications technical data mc68HC908LJ12 ? rev. 2.0 408 mechanical specifications motorola 24.3 52-pin low-profile quad flat pack (lqfp) figure 24-1. 52-pin low-profile quad flat pack (case no. 848d) f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ? h ? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ? l ? , ? m ? and ? n ? to be determined at datum plane ? h ? . 5. dimensions s and v to be determined at seating plane ? t ? . 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ? h ? . 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.46 (0.018). minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). view aa ab ab view y section ab ? ab rotated 90 10.00 bsc 0.394 bsc millimeters a1 5.00 bsc 0.197 bsc b 10.00 bsc 0.394 bsc b1 5.00 bsc 0.197 bsc c ??? 1.70 ??? 0.067 c1 0.05 0.20 0.002 0.008 c2 1.30 1.50 0.051 0.059 d 0.20 0.40 0.008 0.016 e 0.45 0.030 f 0.22 0.35 0.009 0.014 g 0.65 bsc 0.75 0.018 0.026 bsc j 0.07 0.20 0.003 0.008 k 0.50 ref 0.020 ref r1 0.08 0.20 0.003 0.008 s 12.00 bsc 0.472 bsc s1 6.00 bsc 0.236 bsc u 0.09 0.16 0.004 0.006 v 12.00 bsc 0.472 bsc v1 6.00 bsc 0.236 bsc w 0.20 ref 0.008 ref z 1.00 ref 0.039 ref c l ? x ? x=l, m, n 1 13 14 26 27 39 40 52 4x 13 tips 4x n 0.20 (0.008) h l ? m n 0.20 (0.008) t l ? m seating plane c 0.10 (0.004) t 4x s 0.05 (0.002) 0.25 (0.010) gage plane c2 c1 w k e z s l ? m m 0.13 (0.005) n s t plating base metal d j u b v b1 a s v1 a1 s1 ? l ? ? n ? ? m ? ? h ? ? t ? 0 0 0 0 7 12 12 12 12 7 ??? ??? ref ref 3x view y view aa 2x r r1 ref ref f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications 64-pin low-profile quad flat pack (lqfp) mc68HC908LJ12 ? rev. 2.0 technical data motorola mechanical specifications 409 24.4 64-pin low-profile quad flat pack (lqfp) figure 24-2. 64-pin low-profile quad flat pack (case no. 840f) ab ab e/2 e 60x x=a, b or d c l view y s 0.05 0.25 gage plane seating plane a2 (s) r1 2x r (l) (l2) l a1 view aa b1 section ab ? ab b c1 c plating base metal rotated 90 a ? b m 0.08 d c 64 0.2 ha ? bd 1 49 48 17 16 32 33 b e/2 e e1 d1 d/2 d d1/2 3x view y a 4x view aa 0.08 c ( ? 0.2 ca ? bd e1/2 a d c h x dim min max millimeters a ? 1.60 a1 0.05 0.15 a2 1.35 1.45 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 d 12.00 bsc d1 10.00 bsc e 0.50 bsc e 12.00 bsc e1 10.00 bsc l 0.45 0.75 l1 1.00 ref l2 0.50 ref r1 0.10 0.20 s 0.20 ref 0 7 0 ? 12 ref 12 ref notes: 1. dimensions and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane datum h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane datum c. 5. dimensions d and e to be determined at seating plane datum c. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 per side. 7. dimension bdoes not include dambar protrusion. dambar protrusion shall not cause the b dimension to exceed 0.35. minimum space between protrusion and adjacent lead or protrusion 0.07. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications technical data mc68HC908LJ12 ? rev. 2.0 410 mechanical specifications motorola 24.5 64-pin quad flat pack (qfp) figure 24-3. 64-pin quad flat pack (case no. 840b) l l ? a ? ? b ? detail a ? d ? b a s v detail a p b b d ? a ? , ? b ? , ? d ? c ? c ? e h g m m detailc seating plane datum plane 1 16 ? h ? 0.01 (0.004) r detail c datum plane ? h ? t u q k w x s a ? b m 0.20 (0.008) d s h s a ? b m 0.20 (0.008) d s c 0.05 (0.002) a ? b s a ? b m 0.20 (0.008) d s c 0.05 (0.002) a ? b s a ? b m 0.20 (0.008) d s h 48 33 s a ? b m 0.02 (0.008) d s c n f j base metal 32 49 17 64 dim min max min max inches millimeters a 13.90 14.10 0.547 0.555 b 13.90 14.10 0.547 0.555 c 2.15 2.45 0.085 0.096 d 0.30 0.45 0.012 0.018 e 2.00 2.40 0.079 0.094 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h ? 0.25 ? 0.010 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 12.00 ref 0.472 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 p 0.40 bsc 0.016 bsc q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 16.95 17.45 0.667 0.687 t 0.13 ? 0.005 ? u 0 ? 0 ? v 16.95 17.45 0.667 0.687 w 0.35 0.45 0.014 0.018 x 1.6 ref 0.063 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ? h ? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ? a ? , ? b ? and ? d ? to be determined at datum plane ? h ? . 5. dimensions s and v to be determined at seating plane ? c ? . 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ? h ? . 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) per side. total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. section b ? b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908LJ12 ? rev. 2.0 technical data motorola ordering information 411 technical data ? mc68HC908LJ12 section 25. ordering information 25.1 contents 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 25.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 25.2 introduction this section contains ordering numbers for the mc68HC908LJ12. 25.3 mc order numbers table 25-1. mc order numbers mc order number package operating temperature range mc68HC908LJ12cfb 52-pin lqfp ? 40 c to +85 c mc68HC908LJ12cpb 64-pin lqfp ? 40 c to +85 c mc68HC908LJ12cfu 64-pin qfp ? 40 c to +85 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information technical data mc68HC908LJ12 ? rev. 2.0 412 ordering information motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minato-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? typical ? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? typicals ? must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2002 mc68HC908LJ12/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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